KR970051155A - Shared memory controller and method - Google Patents

Shared memory controller and method Download PDF

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Publication number
KR970051155A
KR970051155A KR1019950067869A KR19950067869A KR970051155A KR 970051155 A KR970051155 A KR 970051155A KR 1019950067869 A KR1019950067869 A KR 1019950067869A KR 19950067869 A KR19950067869 A KR 19950067869A KR 970051155 A KR970051155 A KR 970051155A
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South Korea
Prior art keywords
memory
shared memory
selection signal
shared
memory area
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KR1019950067869A
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Korean (ko)
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KR100353448B1 (en
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이승목
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김광호
삼성전자 주식회사
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Publication of KR970051155A publication Critical patent/KR970051155A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술 분야1. TECHNICAL FIELD OF THE INVENTION

공유메모리 제어.Shared memory control.

2. 발명이 해결하려고 하는 기술적 과제.2. The technical problem that the invention is trying to solve.

다수의 프로세서들이 공유하는 메모리를 특정 프로세서에 의해 전용으로 억세스되는 독점메모리와 함께 설계하여 이를 제어한다.The memory shared by multiple processors is controlled by designing with a proprietary memory that is exclusively accessed by a particular processor.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

본 발명에 따른 메모리는 제1선택신호에 의해 선택되며 제1프로세서에 의해 억세스되는 독점메모리 영역 및 제2선택신호에 의해 선택되며 제1및 제2프로세서에 의해 억세스되는 공유메모리 영역으로 구성하고, 제어부가 메모리의 억세스를 제어한다. 이를 위하여 제어부는 제1프로세스가 독점메모리 영역의 사용 요구시 제1선택신호를 발생하여 제1프로세스와 독점메모리 영역 간의 통로를 형성하며, 제1프로세스가 공유메모리 영역의 사용 요구시 제2선택 신호를 발생하여 공유메모리를 활성화시키고 제1프로세서스와 공유메모리를 연결하며, 제2프로세스가 공유메모리 영역의 사용요구시 제2선택신호를 발생하여 공유메모리를 활성화시키고 제2프로세스와 공유메모리를 연결한다.The memory according to the present invention comprises an exclusive memory area selected by the first selection signal and accessed by the first processor and a shared memory area selected by the second selection signal and accessed by the first and second processors, The control unit controls the access of the memory. To this end, the controller generates a first selection signal when the first process requests the use of the exclusive memory area to form a path between the first process and the exclusive memory area, and when the first process requests the use of the shared memory area, the controller selects the second selection signal. Activates the shared memory, connects the first processor and the shared memory, and when the second process requests the use of the shared memory area, generates a second selection signal to activate the shared memory and connects the second process and the shared memory. .

4. 발명의 중요한 용도4. Important uses of the invention

공유메모리 및 독점메모리를 구비하여 기능을 수행하는 시스템에서 하나의 메모리에 독점메모리와 공유메모리를 구성한다.In a system having a shared memory and a proprietary memory and performing a function, the exclusive memory and the shared memory are configured in one memory.

Description

공윤메모리 제어장치 및 방법Gongyun memory control device and method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따라 구현된 공유메모리의 구조 예를 도시한 도면2 is a diagram showing an example of a structure of a shared memory implemented according to the present invention.

Claims (3)

다수의 프로세서들이 메모리를 공유하는 장치에 있어서, 제1선택신호에 의해 선택되며 제1프로세스에 의해 억세스되는 독점메모리 영역 및 제2선택신호에 의해 선택되며 제1및 제2프로세서에 의해 억세스되는 공유메모리 영역으로 구성되는 메모리와, 상기 제1선택신호 및 제2선택신호를 발생하며, 상기 제1선택신호 발생시 제1제어신호 또는 제2제어신호를 발생하는 제어수단과, 상기 제1제어신호 발생시 온되어 상기 제1프로세스와 상기 메모리의 공유메모리 영역을 연결하는 제1수단과, 상기 제2제어신호 발생시 온되어 상기 제2프로세스와 상기 메모리의 공유메모리 영역을 연결하는 제2수단으로 구성되어, 상기 제어수단이 상기 독점메모리 및 공유 메모리를 선택하며, 상기 공유메모리 선택시 다수의 프로세서들의 요구에 따라 해당하는 프로세스와 공유메모리 영역간의 통로를 연결하는 것을 특징으로 하는 공유메모리 제어장치.1. An apparatus in which a plurality of processors share a memory, comprising: an exclusive memory region selected by a first selection signal and accessed by a first process and a shared memory selected by a second selection signal and accessed by a first and a second processor. A memory comprising a memory area, control means for generating the first selection signal and the second selection signal, and generating a first control signal or a second control signal when the first selection signal is generated, and when the first control signal is generated First means for connecting the first process and the shared memory area of the memory, and second means for connecting the second process and the shared memory area of the memory when the second control signal is generated, The control means selects the exclusive memory and the shared memory, and selects the shared memory and the corresponding process according to the request of a plurality of processors when selecting the shared memory. Shared memory control device characterized in that for connecting the passage between shared memory areas. 제1항에 있어서, 상기 메모리가 스테틱 랜덤 액세스 메모리인 것을 특징으로 하는 공유메모리 제어장치.2. The shared memory controller of claim 1, wherein the memory is a static random access memory. 제1선택신호에 의해 선택되며 제1프로세스에 의해 억세스되는 독점메모리 영역 및 제2선택신호에 의해 선택되며 제1및 제2프로세스에 의해 억세스되는 공유메모리 영역으로 구성되는 메모리와, 제1제어신호 발생시 온되어 상기 제1프로세스와 상기 메모리의 공유메모리 영역을 연결하는 제1연결수단과, 제2제어신호 발생시온되어 상기 제2프로세스와 상기 메모리의 공유메모리 영역을 연결하는 제2연결수단을 구비하여 상기 공유메모리의 억세스를 제어하는 방법에 있어서, 상기 제1프로세스가 독점메모리 영역의 사용 요구시 강기 제1연결수단및 제2연결수단을 오프시키고 상기 제1선택신호를 발생하여 상기 제1프로세스와 독점메모리 영역 간의 통로를형성하는 과정과, 상기 제1프로세스가 상기 공유메모리 영역의 사용요구시 상기 제2선택신호 및 상기 제1제어신호르 발생하여 상기 제1프로세스의 상기 공유메모리를 연결하는 과정과, 상기 제2프로세스가 상기 공유메모리 영역의 사용요구시 상기 제2선택신호 및 상기 제2제어신호를 발생하여 상기 제2프로세스와 상기 공유메모리를 연결하는 과정으로 이루어짐을 특징으로 하는 공유메모리의 제어방법.A memory comprising an exclusive memory area selected by the first selection signal and accessed by the first process and a shared memory area selected by the second selection signal and accessed by the first and second processes, and a first control signal First connection means which is turned on when the first process is connected to the shared memory area of the memory, and second connection means which is turned on when the second control signal is generated and connects the second process and the shared memory area of the memory; 1. The method of controlling access of the shared memory, wherein the first process turns off the first connection means and the second connection means when a request for the use of the exclusive memory area is generated, and generates the first selection signal to generate the first process. Forming a path between the memory area and an exclusive memory area; and when the first process requests the use of the shared memory area, the second selection signal and image; Generating a first control signal to connect the shared memory of the first process; and generating a second selection signal and the second control signal when the second process requests the use of the shared memory area. 2 process and the process of connecting the shared memory control method of a shared memory. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950067869A 1995-12-30 1995-12-30 Apparatus and method for controlling shared memory KR100353448B1 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100725099B1 (en) * 2005-12-22 2007-06-04 삼성전자주식회사 Memory expansion structure in multi-path accessible semiconductor memory device
KR100725100B1 (en) * 2005-12-22 2007-06-04 삼성전자주식회사 Multi-path accessible semiconductor memory device having data transfer mode between ports
KR100850277B1 (en) * 2006-11-15 2008-08-04 삼성전자주식회사 Bank addresses assign method for use in multi-path accessible semiconductor memory device
US7870326B2 (en) 2006-07-28 2011-01-11 Samsung Electronics Co., Ltd. Multiprocessor system and method thereof

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100591371B1 (en) * 2005-03-23 2006-06-20 엠텍비젼 주식회사 Method for varying size of partitioned blocks of shared memory and portable terminal having shared memory
KR100735612B1 (en) 2005-12-22 2007-07-04 삼성전자주식회사 Multi-path accessible semiconductor memory device
KR100813133B1 (en) 2006-11-22 2008-03-17 엠텍비젼 주식회사 Dual port memory apparatus, memory system and method for adaptive using shared memory area of dual port memory apparatus

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100725099B1 (en) * 2005-12-22 2007-06-04 삼성전자주식회사 Memory expansion structure in multi-path accessible semiconductor memory device
KR100725100B1 (en) * 2005-12-22 2007-06-04 삼성전자주식회사 Multi-path accessible semiconductor memory device having data transfer mode between ports
US7984261B2 (en) 2005-12-22 2011-07-19 Samsung Electronics Co., Ltd. Memory expansion structure in multi-path accessible semiconductor memory device
US7870326B2 (en) 2006-07-28 2011-01-11 Samsung Electronics Co., Ltd. Multiprocessor system and method thereof
KR100850277B1 (en) * 2006-11-15 2008-08-04 삼성전자주식회사 Bank addresses assign method for use in multi-path accessible semiconductor memory device

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