KR970049471A - Board selector of communication module - Google Patents

Board selector of communication module Download PDF

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Publication number
KR970049471A
KR970049471A KR1019950054761A KR19950054761A KR970049471A KR 970049471 A KR970049471 A KR 970049471A KR 1019950054761 A KR1019950054761 A KR 1019950054761A KR 19950054761 A KR19950054761 A KR 19950054761A KR 970049471 A KR970049471 A KR 970049471A
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KR
South Korea
Prior art keywords
board
communication module
address
upper processor
vme
Prior art date
Application number
KR1019950054761A
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Korean (ko)
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KR100414922B1 (en
Inventor
이재현
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950054761A priority Critical patent/KR100414922B1/en
Publication of KR970049471A publication Critical patent/KR970049471A/en
Application granted granted Critical
Publication of KR100414922B1 publication Critical patent/KR100414922B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Multi Processors (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

통신 모듈의 보드 선택장치Board selector of communication module

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

상위 프로세서와 하위 프로세서들의 보드들로 구성되는 통신 모듈에서 하위 프로세서들이 보드 식별정보를 이용하여 어드레스를 비교한다.In a communication module consisting of boards of an upper processor and lower processors, lower processors compare addresses using board identification information.

3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention

VME버스에 연결되는 상위 프로세서와 다수의 하위 프로세서들로 이루어지는 통신 모듈의 보드 선택장치가, 하위 프로세서들을 선택하기 위한 VME 어드레스를 발생하는 상위 프로세서와, 백보드에 세팅된 보드 식별정보를 로컬 어드레스로 변환하는 수단과, 로컬 어드레스와 VME 어드레스를 비교하여 동일할 시 매치신호를 발생하는 수단을 구비하며, 상위 프로세서의 선택에 의해 해당 어드레스 영역의 데이타가 억세스되는 하위 프로세서들로 구성된다.The board selector of the communication module, which is composed of an upper processor connected to the VME bus and a plurality of lower processors, converts an upper processor that generates a VME address for selecting lower processors, and board identification information set on the backboard into a local address. Means for comparing the local address with the VME address, and generating a match signal when they are identical, and comprising lower processors for which data in the corresponding address area is accessed by selection of an upper processor.

4. 발명의 중요한 용도4. Important uses of the invention

하위 프로세서들이 보드 식별정보를 이용하므로서, 별도의 로컬 어드레스 발생 수단을 사용하지 않는다.Since lower processors use the board identification information, they do not use a separate local address generation means.

Description

통신 모듈의 보드 선택장치Board selector of communication module

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 VME버스에 연결되는 상위 프로세서와 하위 프로세서들로 구성되는 통신 모듈에서 상위 프로세서가 하위 프로세서들을 선택하는 종래의 동작을 설명하기 위한 도면,1 is a view for explaining a conventional operation of the upper processor selects the lower processor in the communication module consisting of the upper processor and lower processors connected to the VME bus,

제2도는 제1도에서 하위 프로세서 보드의 어드레스 비교회로의 구성을 도시하는 도면,2 is a diagram showing the configuration of an address comparison circuit of a lower processor board in FIG. 1;

제3도는 VME버스에 연결되는 상위 프로세서와 하위 프로세서들로 구성되는 통신 모듈에서 상위 프로세서가 하위 프로세서들을 선택하는 본 발명의 동작을 설명하기 위한 도면,3 is a diagram for explaining an operation of the present invention in which an upper processor selects lower processors in a communication module including upper and lower processors connected to a VME bus;

제4도는 제3도에서 하위 프로세서 보드의 어드레스 비교회로의 구성을 도시하는 도면.4 is a diagram showing the configuration of an address comparison circuit of a lower processor board in FIG.

Claims (1)

VME버스에 연결되는 상위 프로세서와 다수의 하위 프로세서들로 이루어지는 통신 모듈의 보드 선택장치에 있어서, 상기 하위 프로세스들을 선택하기 위한 VME 어드레스를 발생하는 상위 프로세서와, 백보드에 세팅된 보드 식별정보를 로컬 어드레스로 변화하는 수단과, 상기 로컬 어드레스와 상기 VME 어드레스를 비교하여 동일할 시 매치신호를 발생하는 수단을 구비하며, 상기 상위 프로세서의 선택에 의해 해당 어드레스 영역의 데이타가 억세스되는 하위 프로세서들로 구성된 것을 특징으로 하는 통신 모듈의 보드 선택장치.A board selection apparatus of a communication module comprising an upper processor connected to a VME bus and a plurality of lower processors, the board selecting apparatus comprising: an upper processor generating a VME address for selecting the lower processes, and a board identification information set on a back board; Means for varying the local address, and means for comparing the local address with the VME address and generating a match signal when they are identical, wherein the lower processor is configured to access data in the corresponding address area by selection of the upper processor. Board selector of the communication module characterized in that. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950054761A 1995-12-22 1995-12-22 Device for selecting board of communication module KR100414922B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950054761A KR100414922B1 (en) 1995-12-22 1995-12-22 Device for selecting board of communication module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950054761A KR100414922B1 (en) 1995-12-22 1995-12-22 Device for selecting board of communication module

Publications (2)

Publication Number Publication Date
KR970049471A true KR970049471A (en) 1997-07-29
KR100414922B1 KR100414922B1 (en) 2004-03-27

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Application Number Title Priority Date Filing Date
KR1019950054761A KR100414922B1 (en) 1995-12-22 1995-12-22 Device for selecting board of communication module

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100798583B1 (en) * 2001-12-07 2008-01-28 엘지전자 주식회사 Apparatus and method of serial communication interface

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03100853A (en) * 1989-09-14 1991-04-25 Nec Corp Inter-processor communication system
JPH05507572A (en) * 1990-06-07 1993-10-28 エルジー・セミコン・カンパニー・リミテッド Method and apparatus for managing page zero memory access in a multiprocessor system
JPH04149658A (en) * 1990-10-08 1992-05-22 Canon Inc Information processor
JPH05265967A (en) * 1992-03-16 1993-10-15 Fujitsu Ltd Data communicating method for multi-processor system
KR0122321Y1 (en) * 1993-06-08 1998-09-15 이희종 The arbiter of memory access in multiprocessor system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100798583B1 (en) * 2001-12-07 2008-01-28 엘지전자 주식회사 Apparatus and method of serial communication interface

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