KR970049109A - Sorter interface method using memory - Google Patents

Sorter interface method using memory Download PDF

Info

Publication number
KR970049109A
KR970049109A KR1019950058703A KR19950058703A KR970049109A KR 970049109 A KR970049109 A KR 970049109A KR 1019950058703 A KR1019950058703 A KR 1019950058703A KR 19950058703 A KR19950058703 A KR 19950058703A KR 970049109 A KR970049109 A KR 970049109A
Authority
KR
South Korea
Prior art keywords
data
interface
memory
sorter
central processing
Prior art date
Application number
KR1019950058703A
Other languages
Korean (ko)
Other versions
KR0174398B1 (en
Inventor
김정호
Original Assignee
우석형
주식회사 신도리코
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 우석형, 주식회사 신도리코 filed Critical 우석형
Priority to KR1019950058703A priority Critical patent/KR0174398B1/en
Publication of KR970049109A publication Critical patent/KR970049109A/en
Application granted granted Critical
Publication of KR0174398B1 publication Critical patent/KR0174398B1/en

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03GELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
    • G03G15/00Apparatus for electrographic processes using a charge pattern
    • G03G15/50Machine control of apparatus for electrographic processes using a charge pattern, e.g. regulating differents parts of the machine, multimode copiers, microprocessor control
    • G03G15/5016User-machine interface; Display panels; Control console
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03GELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
    • G03G15/00Apparatus for electrographic processes using a charge pattern
    • G03G15/65Apparatus which relate to the handling of copy material
    • G03G15/6538Devices for collating sheet copy material, e.g. sorters, control, copies in staples form
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03GELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
    • G03G2215/00Apparatus for electrophotographic processes
    • G03G2215/00362Apparatus for electrophotographic processes relating to the copy medium handling
    • G03G2215/00367The feeding path segment where particular handling of the copy medium occurs, segments being adjacent and non-overlapping. Each segment is identified by the most downstream point in the segment, so that for instance the segment labelled "Fixing device" is referring to the path between the "Transfer device" and the "Fixing device"
    • G03G2215/00417Post-fixing device
    • G03G2215/00421Discharging tray, e.g. devices stabilising the quality of the copy medium, postfixing-treatment, inverting, sorting

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Collation Of Sheets And Webs (AREA)

Abstract

본 발명은 소터(Sorter)의 제어회로와 복사기 본체 제어회로간의 인터페이스를 메모리(RAM)를 이용해서 구현하는 메모리를 이용한 소터의 인테페이스 방법에 관한 것으로, 본 발명에서는 일반 메모리 억세스 기법을 사용함에 따라 가로채기(INTERRUPT)에 의한 종래의 인터페이스 방법에 비해, 인터페이스 루틴이 정기적으로 수행되도록 하므로서, 소프트웨어의 부담을 경감시키고, PUSH와 POP 등에 요하던 임시 저장용 메모리를 배제시킬 뿐만아니라, 인터페이스용 메모리 공유로 인한 데이터 파손도 방지하는 메모리를 이용한 소터의 인터페이스 방법을 제공한다.The present invention relates to a sorter interface method using a memory that implements an interface between a sorter control circuit and a copier main body control circuit using a memory (RAM). Compared to the conventional interface method by INTERRUPT, the interface routine is executed regularly, thereby reducing the burden on software, eliminating the temporary storage memory required for PUSH and POP, and sharing the memory for the interface. It also provides a sorter interface method using memory that prevents data corruption.

Description

메모리를 이용한 소터의 인터페이스 방법Sorter interface method using memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명이 적용되는 소터의 개략적인 하드웨어 구성을 나타낸 블록도.3 is a block diagram showing a schematic hardware configuration of a sorter to which the present invention is applied.

제4도는 본 발명에 의한 소터 인터페이스 방법의 일실시예 수행과정을 나타낸 흐름도.4 is a flowchart illustrating an embodiment of a sorter interface method according to the present invention.

Claims (2)

소터의 제반 동작을 제어하기 위한 중앙처리 수단(11)과, 상기 중앙 처리 수단(11) 및 복사기 본체의 제어보드간에 연결된 인터페이스 메모리(12)를 구비하고 있는 소터의 인터페이스 방법에 있어서, 상기 중앙처리 수단의 CPU(Central Processing Unit) 레지스터 또는 메모리 클리어 등을 수행하여 초기화하는 제 1단계(301); 상기 소터의 모드와 각 감지 수단들(15, 16, 17)의 신호에 따라 상기 중앙처리 수단(11)의 제어하에 동작하는 주변 구동부들(13, 14)을 작동시켜 기본처리루틴을 수행하는(302) 제 2단계; 상기 인터페이스 메모리(12)로부터 수신할 데이터 유무의 정보를 읽어(303), 인터페이스 수신 데이터의 유무를 판단하는(304) 제3단계; 인터페이스 송신 데이터가 있는지 여부를 확인하는(307) 제 4단계; 및 상기 제 4단계의 판단결과, 송신할 데이타가 없으면 다시 상기 제 2단계의 기본처리루틴(302)으로 복귀해서 기본처리루틴 부터 반복수행하고, 송신할 데이타가 있으면 상기 인터페이스 메모리(12)에 송신 데이타를 쓰기(WRITE)한 후(308), 상기 기본처리루틴(302)으로 복귀해서 상기 기본처리루틴 부터 반복수행하는 제5단계를 포함하는 것을 특징으로 하는 메모리를 이용한 소터의 인터페이스 방법.A central processing means (11) for controlling the overall operation of a sorter and an interface memory (12) connected between the central processing means (11) and the control board of the copier main body, wherein the central processing method of the sorter comprises: A first step 301 of initializing by performing a CPU (Central Processing Unit) register or a memory clear of the means; In accordance with the mode of the sorter and the signals of the respective sensing means 15, 16, 17, peripheral driving units 13 and 14 operating under the control of the central processing unit 11 are operated to perform basic processing routines ( 302) second step; Reading (303) information on the presence or absence of data to be received from the interface memory (12) and determining (304) whether interface reception data is present; A fourth step of checking whether there is interface transmission data (307); And if there is no data to be transmitted, the process returns to the basic processing routine 302 of the second stage and repeats from the basic processing routine. If there is data to be transmitted, the data is transmitted to the interface memory 12. And a fifth step of writing data (WRITE) to the basic processing routine (302) and repeating from the basic processing routine. 제1항에 있어서, 상기 제 3단계에서의 인터페이스 수신 데이터 유무 판단결과(304), 수신 데이터가 있는 것으로 판단되면, 상기 제 4단계 수행직전에 수행되되, 상기 인터페이스 메모리(12)로부터 읽어들인 데이터를 분석해서(305), 상기 기본처리루틴에서 사용할 수 있도록 그 데이터를 변환하는(306) 제 6단계를 더 포함하는 것을 특징으로 하는 메모리를 이용한 소터의 인터페이스 방법.The data read from the interface memory 12 according to claim 1, wherein the determination result of the presence or absence of the interface reception data 304 in the third step is performed immediately before the fourth step is performed if it is determined that there is received data. And a sixth step of analyzing (305) and converting (306) its data for use in the basic processing routine. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950058703A 1995-12-27 1995-12-27 Sorter interface method using memory KR0174398B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950058703A KR0174398B1 (en) 1995-12-27 1995-12-27 Sorter interface method using memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950058703A KR0174398B1 (en) 1995-12-27 1995-12-27 Sorter interface method using memory

Publications (2)

Publication Number Publication Date
KR970049109A true KR970049109A (en) 1997-07-29
KR0174398B1 KR0174398B1 (en) 1999-04-01

Family

ID=19445058

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950058703A KR0174398B1 (en) 1995-12-27 1995-12-27 Sorter interface method using memory

Country Status (1)

Country Link
KR (1) KR0174398B1 (en)

Also Published As

Publication number Publication date
KR0174398B1 (en) 1999-04-01

Similar Documents

Publication Publication Date Title
KR930018378A (en) Method and device for performance optimization of cache memory system
KR950033803A (en) Multiple bit shift device, data processor using same, and multiple bit shift method
KR950015397A (en) Multi-bit Test Circuit and Method of Semiconductor Memory Device
KR970049109A (en) Sorter interface method using memory
KR950015104A (en) How to support indivisible cycle using bus monitor
EP0463352A2 (en) Microprocessor for use in in-circuit emulator having function of discriminating users space and in-circuit emulator space
KR970049813A (en) Circuits and Methods for Evaluating Fuzzy Logic Rules
KR960042393A (en) Interface device between general purpose measuring instrument and processing system
SU1236560A1 (en) Storage
KR970012172A (en) BUS CONTROLLER DEVICE FOR MULTI-Microprocessors
KR920022751A (en) How to Select Monetary Bus for Lower Level Processors
KR960025127A (en) Method and circuit using part of memory as input / output buffer
JPH03108022A (en) Semiconductor integrated circuit
JPH10240416A (en) Keyboard device
JPS6049465A (en) Data transfer method between microcomputers
KR950006568A (en) Memory backup circuit
KR890003541A (en) Word unit printing method of electronic typewriter
KR930014093A (en) How to perform read command between RPU and CIP
KR920010408A (en) How to select screen properties on display terminal
KR960025196A (en) Operation processing method of image data
KR950022446A (en) Variable connection between ATM layer and upper layer
KR940018773A (en) Document recognition device and document recognition control method
JPH02224539A (en) Alarm signal generating system
KR880009300A (en) Arithmetic processing unit
KR940006772A (en) Reversed argument method of printer

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20021104

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee