KR970030721A - Semiconductor substrate bumps and manufacturing method thereof - Google Patents

Semiconductor substrate bumps and manufacturing method thereof Download PDF

Info

Publication number
KR970030721A
KR970030721A KR1019950043743A KR19950043743A KR970030721A KR 970030721 A KR970030721 A KR 970030721A KR 1019950043743 A KR1019950043743 A KR 1019950043743A KR 19950043743 A KR19950043743 A KR 19950043743A KR 970030721 A KR970030721 A KR 970030721A
Authority
KR
South Korea
Prior art keywords
bump
semiconductor substrate
pad
conductive material
protective film
Prior art date
Application number
KR1019950043743A
Other languages
Korean (ko)
Other versions
KR0171099B1 (en
Inventor
김성진
Original Assignee
구자홍
엘지전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 구자홍, 엘지전자 주식회사 filed Critical 구자홍
Priority to KR1019950043743A priority Critical patent/KR0171099B1/en
Priority to US08/755,142 priority patent/US6232563B1/en
Publication of KR970030721A publication Critical patent/KR970030721A/en
Application granted granted Critical
Publication of KR0171099B1 publication Critical patent/KR0171099B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 반도체 기판 범프 및 제조 방법에 관한 것으로 범프를 통한 본딩시 발생되던 전기적 단락 문제를 해결하기에 적합하도록 반도체 기판과, 반도체 기판 상에 형성된 패드와, 패드의 일부와 패드가 형성되지 않은 기판 영역을 보호하기 위해 형성된 보호막과, 패드 상부의 보호막 위와 보호막으로 부터 노출된 패드 위에 형성된 확산방지층과, 확산방지층의 상부에 형성된 범프를 포함하는 반도체 기판 범프에 있어서, 범프는 상기 측면에 산화막이 형성된 제 1범프와, 제1범프의 상면에 형성된 제 2범프로 이루어지며, 이러한 범프는 제 1범프의 상면의 제 2범프에 비해 산화성이 강한 물질로 형성하여 종래의 범프 제조방법에서 마스크 추가없이 산화작업을 추가함으로써 반도체 기판 범프를 제조한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate bump and a manufacturing method. A semiconductor substrate bump comprising a protective film formed to protect an area, a diffusion barrier layer formed on the protective film on the pad top and on a pad exposed from the protective film, and a bump formed on the diffusion barrier layer, wherein the bump is formed with an oxide film formed on the side surface. It is composed of the first bump and the second bump formed on the upper surface of the first bump, the bump is formed of a material that is more oxidative than the second bump on the upper surface of the first bump to oxidize without adding a mask in the conventional bump manufacturing method By adding work, a semiconductor substrate bump is produced.

Description

반도체 기판 범프 및 그 제조방법Semiconductor substrate bumps and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 3도는 본 발명의 반도체 기판 범프의 구조와 제조방법의 각 공정을 예시한 단면도.3 is a cross-sectional view illustrating each step of the structure and manufacturing method of the semiconductor substrate bump of the present invention.

제 4도는 본 발명의 반도체 기판 범프의 실제 본딩 상태를 예시한 단면도.4 is a cross-sectional view illustrating the actual bonding state of the semiconductor substrate bump of the present invention.

Claims (9)

반도체 기판과, 상기 반도체 기판 상에 형성된 패드와, 상기 패드의 일부가 노출되게 상기 기판위에 형성된 보호막과, 상기 보호막으로부터 노출된 패드 위에 형성된 확산방지층과, 상기 확산방지층의 상부에 형성된 범프를 포함하는 반도체 기판 범프에 있어서, 상기 범프는 측면이 산화막이 형성된 제 1범프와, 상기 제 1범프의 상면에 형성된 제 2범프로 이루어진 것을 특징으로 하는 반도체 기판 범프.A semiconductor substrate, a pad formed on the semiconductor substrate, a protective film formed on the substrate to expose a portion of the pad, a diffusion barrier layer formed on the pad exposed from the protective film, and a bump formed on the diffusion barrier layer The semiconductor substrate bump according to claim 1, wherein the bump is formed of a first bump having an oxide film on a side thereof and a second bump formed on an upper surface of the first bump. 제 1항에 있어서, 상기 제 1범프는 제 2범프보다 산화성이 강한 금속으로 이루어진 것을 특징으로 하는 반도체 기판 범프.The semiconductor substrate bump of claim 1, wherein the first bump is made of a metal that is more oxidative than the second bump. 제 1항에 있어서, 상기 제 1범프는 Ni, Al, Cu중 한 물질로 이루어진 것을 특징으로 하는 반도체 기판 범프.The semiconductor substrate bump of claim 1, wherein the first bump is made of one of Ni, Al, and Cu. 제 1항에 있어서, 상기 제 2범프는 내산화성 금속으로 이루어진 것을 특징으로 하는 반도체 기판 범프.The semiconductor substrate bump of claim 1, wherein the second bump is made of an oxide resistant metal. 반도체기판 상부에 패드를 형성하고, 패드 및 기판위에 보호막을 적층한 후, 패드의 일부영역을 노출시키는 단계와, 상기 노출된 패드와 상기 보호막 위에 확산방지층을 형성하는 단계와, 상기 노출된 패드 상부의 확산방지층이 노출되도록 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트 패턴을 이용하여 제 1도전물질로 제 1범프를 형성하는 단계와, 상기 포토레지스트 패턴을 이용하여 제 2도전물질로 상기 제 1범프 위에 제 2범프를 형성하는 단계와, 상기 포토레지스트 패턴을 제거하고, 상기 제 1범프를 산화시켜, 상기 제 1범프 측면에 산화막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 기판 범프 제조방법.Forming a pad on the semiconductor substrate, stacking a protective film on the pad and the substrate, exposing a portion of the pad, forming a diffusion barrier layer on the exposed pad and the protective film, and Forming a photoresist pattern to expose the diffusion barrier layer of the photoresist, forming a first bump using the photoresist pattern as a first conductive material, and using the photoresist pattern as the second conductive material as the second conductive material. Forming a second bump on one bump, removing the photoresist pattern, and oxidizing the first bump to form an oxide film on the side of the first bump. Way. 제 5항에 있어서, 상기 제 1도전물질은 상기 제 2도전물질보다 산화성이 강한 물질인 것을 특징으로 하는 반도체 기판 범프 제조방법.6. The method of claim 5, wherein the first conductive material is a material that is more oxidative than the second conductive material. 제 5항에 있어서, 상기 제 범프 및 제 2범프를 전기 도금 방법으로 형성하는 것을 특징으로 하는 반도체 기판 범프 제조방법.6. The method of claim 5, wherein the first bump and the second bump are formed by an electroplating method. 제 5항에 있어서, 상기 제 1도전물질은 Ni, Al, Cu 중 하나인 것을 특징으로 하는 반도체 기판 범프 제조방법.The method of claim 5, wherein the first conductive material is one of Ni, Al, and Cu. 제 5항에 있어서, 상기 제 2도전물질은 Au인 것을 특징으로 하는 반도체 기판 범프 제조방법.6. The method of claim 5, wherein the second conductive material is Au. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950043743A 1995-11-25 1995-11-25 Substrate bumb and the same manufacture method KR0171099B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019950043743A KR0171099B1 (en) 1995-11-25 1995-11-25 Substrate bumb and the same manufacture method
US08/755,142 US6232563B1 (en) 1995-11-25 1996-11-22 Bump electrode and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950043743A KR0171099B1 (en) 1995-11-25 1995-11-25 Substrate bumb and the same manufacture method

Publications (2)

Publication Number Publication Date
KR970030721A true KR970030721A (en) 1997-06-26
KR0171099B1 KR0171099B1 (en) 1999-02-01

Family

ID=19435727

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950043743A KR0171099B1 (en) 1995-11-25 1995-11-25 Substrate bumb and the same manufacture method

Country Status (1)

Country Link
KR (1) KR0171099B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW464927B (en) 2000-08-29 2001-11-21 Unipac Optoelectronics Corp Metal bump with an insulating sidewall and method of fabricating thereof
KR100455387B1 (en) * 2002-05-17 2004-11-06 삼성전자주식회사 Method for forming a bump on semiconductor chip and COG package including the bump

Also Published As

Publication number Publication date
KR0171099B1 (en) 1999-02-01

Similar Documents

Publication Publication Date Title
KR950007059A (en) integrated circuit
KR950004464A (en) Manufacturing method of chip bump
KR980005659A (en) Semiconductor device and manufacturing method thereof
KR960019684A (en) Lead frame and manufacturing method
KR960012334A (en) Semiconductor chip cuff erase method and semiconductor chip and electronic module formed therefrom
KR940016513A (en) Low resistance contact formation method of semiconductor device
US6555925B1 (en) Semiconductor device and producing method thereof
KR980005302A (en) Contact mask for semiconductor device manufacturing
KR970053198A (en) Bonding device for semiconductor device and manufacturing method thereof
KR970030721A (en) Semiconductor substrate bumps and manufacturing method thereof
EP1148559A3 (en) High speed semiconductor photodetector and method of fabricating the same
KR930020590A (en) Etching method of metal thin film mainly composed of aluminum and manufacturing method of thin film transistor
KR970053159A (en) Semiconductor substrate bumps and manufacturing method thereof
KR880014660A (en) Semiconductor device manufacturing method
KR920013788A (en) Improved method for fabricating Schottky barrier diodes in a single polybipolar process
KR910005458A (en) Manufacturing Method of Semiconductor Equipment
KR980005930A (en) Semiconductor device and manufacturing method
KR910019194A (en) Semiconductor device and manufacturing method
KR920003532A (en) Manufacturing Method of Semiconductor Integrated Circuit in Master Slice Method
KR980006145A (en) Semiconductor device and manufacturing method thereof
JPS6180836A (en) Semiconductor device having multilayer interconnection
KR940010302A (en) Semiconductor connection device
JPS6074658A (en) Semiconductor ic device
KR940010284A (en) Bump Formation Method of Semiconductor Device
KR960026409A (en) Semiconductor integrated circuit device with wiring structure effective for migration and mask misalignment and manufacturing method

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20061002

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee