KR970029780A - Erasing Verification Method of Flash Memory Using Bitline Precharge Level - Google Patents

Erasing Verification Method of Flash Memory Using Bitline Precharge Level Download PDF

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Publication number
KR970029780A
KR970029780A KR1019950040701A KR19950040701A KR970029780A KR 970029780 A KR970029780 A KR 970029780A KR 1019950040701 A KR1019950040701 A KR 1019950040701A KR 19950040701 A KR19950040701 A KR 19950040701A KR 970029780 A KR970029780 A KR 970029780A
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KR
South Korea
Prior art keywords
precharge level
flash memory
bitline
bit line
reference voltage
Prior art date
Application number
KR1019950040701A
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Korean (ko)
Inventor
이동기
Original Assignee
김광호
삼성전자 주식회사
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950040701A priority Critical patent/KR970029780A/en
Publication of KR970029780A publication Critical patent/KR970029780A/en

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Abstract

본 발명은 접힘 비트라인(Folded bitline) 구조를 가진 낸드(NAND)형 플래쉬 메모리의 비트라인 선충전 레벨을 이용한 소거검증 방법에 관한 것으로서, 초기 비트라인 선충전 레벨을 다르게 하여 이 레벨을 기준전압 Vref1, Vref2 두개로 각각 분리하여, 정상읽기시에는 기준전압을 Vref1으로 하고 소거검증시에는 기준 전압을 Vref2로 각각 제어하여, 소거검증시의 기준 비트라인 전압(Vbl_ref1)과 정상읽기시의 기준 비트라인 전압(Vbl_ref2)을 서로 다르게 하여 센싱 마진을 크게 함을 특징으로 한다.The present invention relates to an erase verification method using a bit line precharge level of a NAND type flash memory having a folded bitline structure, wherein the initial bitline precharge level is changed to refer to the reference voltage Vref1. In this case, the reference voltage is set to Vref1 for normal reading and the reference voltage is set to Vref2 for erasing verification. The reference bitline voltage (Vbl_ref1) for erasing verification and the reference bitline for normal reading are respectively separated. The sensing margin is increased by varying the voltages Vbl_ref2.

본 발명에 의하면 플래쉬 메모리의 소거검증을 행할 때 서로 다른 선충전 레벨차에 의해 develop되는 비트라인 레벨차이를 이용함으로써 보다 안정적인 소거셀에 대한 셍싱 마진을 얻을 수 있게 되어 읽기수행때의 소거 안된 셀에 의한 오동작을 방지할 수 있다.According to the present invention, when performing erase verification of a flash memory, by using bit line level differences developed by different precharge level differences, a more stable aging index for an erased cell can be obtained. Malfunction caused by this can be prevented.

Description

비트라인 선충전 레벨을 이용한 플래쉬 메모리의 소거검증 방법Erasing Verification Method of Flash Memory Using Bitline Precharge Level

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 소거검증 방법을 설명하기 의해 도시한 회로 구성도.2 is a circuit configuration diagram shown by explaining the erase verification method of the present invention.

제3도는 셀소거 검증시의 Pass/Fail 마진을 도시한 마진도.3 is a margin diagram showing a pass / fail margin at the time of cell erasure verification.

제4도는 본 발명에서 사용하는 Vrefl, Vref2의 제어블럭을 도시한 블럭도.4 is a block diagram showing a control block of Vrefl and Vref2 used in the present invention.

Claims (2)

접힘 비트라인(Folded bitline) 구조를 가진 낸드(NAND)형 플래쉬 메모리의 비트라인 선충전 레벨을 이용한 소거검증 방법에 있어서, 초기 비트라인 선충전 레벨을 다르게 하여 이 레벨을 기준전압 Vref1, Vref2 두개로 각각 분리하여, 정상읽기시에는 기준전압을 Vref1으로 하고 소거검증시에는 기준 전압을 Vref2로 각각 제어하여, 소거검증시의 기준 비트라인 전압(Vbl_ref1)과 정상읽기시의 기준 비트라인 전압(Vb1_ref2)을 서로 다르게 하여 센싱 마진을 크게 함을 특징으로 하는 비트라인 선충전 레벨을 이용한 플래쉬 메모리의 소거검증방법.In the erase verification method using the bit line precharge level of a NAND flash memory having a folded bitline structure, the initial bit line precharge level is changed to two reference voltages Vref1 and Vref2. Separately, the reference voltage is set to Vref1 for normal reading and the reference voltage is set to Vref2 for erasing verification. The reference bitline voltage Vbl_ref1 for erasure verification and reference bitline voltage Vb1_ref2 for normal reading are respectively controlled. The erase verification method of the flash memory using the bit line precharge level, characterized in that to increase the sensing margin by different. 제1항에 있어서, 상기 소거검증용 기준전압(Vref2)이 상기 정상읽기용 기준전압(Vref1) 보다 전압레벨이 낮게 제어됨을 특징으로 하는 비트라인 선충전 레벨을 이용한 플래쉬 메모리의 소거검증방법.2. The erase verification method of a flash memory using a bit line precharge level according to claim 1, wherein the erase verification reference voltage (Vref2) is controlled to have a lower voltage level than the normal read reference voltage (Vref1). ※ 참고사항:최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950040701A 1995-11-10 1995-11-10 Erasing Verification Method of Flash Memory Using Bitline Precharge Level KR970029780A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950040701A KR970029780A (en) 1995-11-10 1995-11-10 Erasing Verification Method of Flash Memory Using Bitline Precharge Level

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Application Number Priority Date Filing Date Title
KR1019950040701A KR970029780A (en) 1995-11-10 1995-11-10 Erasing Verification Method of Flash Memory Using Bitline Precharge Level

Publications (1)

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KR970029780A true KR970029780A (en) 1997-06-26

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020006060A (en) * 2000-07-11 2002-01-19 박종섭 Reference voltage generator
US9218887B2 (en) 2013-09-27 2015-12-22 SK Hynix Inc. Nonvolatile semiconductor memory device capable of improving retention/disturb characteristics of memory cells and method of operating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020006060A (en) * 2000-07-11 2002-01-19 박종섭 Reference voltage generator
US9218887B2 (en) 2013-09-27 2015-12-22 SK Hynix Inc. Nonvolatile semiconductor memory device capable of improving retention/disturb characteristics of memory cells and method of operating the same

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