KR970029099A - Real time interfacing method between emulator and host - Google Patents

Real time interfacing method between emulator and host Download PDF

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Publication number
KR970029099A
KR970029099A KR1019950042988A KR19950042988A KR970029099A KR 970029099 A KR970029099 A KR 970029099A KR 1019950042988 A KR1019950042988 A KR 1019950042988A KR 19950042988 A KR19950042988 A KR 19950042988A KR 970029099 A KR970029099 A KR 970029099A
Authority
KR
South Korea
Prior art keywords
emulator
host
real time
real
interfacing
Prior art date
Application number
KR1019950042988A
Other languages
Korean (ko)
Other versions
KR0184454B1 (en
Inventor
유재욱
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950042988A priority Critical patent/KR0184454B1/en
Publication of KR970029099A publication Critical patent/KR970029099A/en
Application granted granted Critical
Publication of KR0184454B1 publication Critical patent/KR0184454B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/105—Program control for peripheral devices where the programme performs an input/output emulation function
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers

Abstract

1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

데이타 처리 시스템.Data processing system.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

디에스피를 가지는 에뮬레이터와 호스트간의 실시간 인터페이싱 방법을 제공함에 있다.The present invention provides a method for real-time interfacing between an emulator having a DSP and a host.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

본 발명은 에뮬레이터와 호스트간에 디에스피가 처리하고자 하는 데이타를 실시간으로 인터페이스할 수 있게 해주는 메모리 버퍼를 통한 실시간 인터페이싱 방법임을 특징으로 한다.The present invention is characterized by a real-time interfacing method through a memory buffer that enables the DSP to interface data to be processed between the emulator and the host in real time.

4.발명의 중요한 용도4. Important uses of the invention

에뮬레이터와 호스트간의 실시간 인터페이싱 방법.Real time interfacing method between emulator and host.

Description

에뮬레이터와 호스트간의 실시간 인터페이싱 방법Real time interfacing method between emulator and host

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 에뮬레이터와 호스트간의 실시간 인터페이싱 방법을 설명하기 위해 제시된 회로블럭도,2 is a circuit block diagram for explaining a real-time interfacing method between an emulator and a host according to the present invention;

제4도는 본 발명의 데이타 인터페이스의 상태 천이 다이아그램.4 is a state transition diagram of a data interface of the present invention.

Claims (2)

에뮬레이터와 호스트간의 인터페이싱 방법에 있어서, 상기 에뮬레이터와 호스트간에 디에스피가 처리하고자 하는 데이타를 실시간으로 인터페이스할 수 있게 해주기 위해 메모리 버퍼를 이용하는 것을 특징으로 하는 방법.A method of interfacing between an emulator and a host, the method comprising using a memory buffer to enable the DSP to interface data in real time between the emulator and the host. 타겟 보드를 포함하는 데이타 처리 시스템의 에뮬레이터와 호스트간의 인터페이싱 방법에 있어서, 상기 에뮬레이터와 호스트간에 디에스피가 처리하고자 하는 데이타를 실시간으로 인터페이스할 수 있게 해주기 위해, 버퍼 메모리를 억세스하는 상태를 제어하는 상태 머시인을 사용하여 인터페이싱하는 것을 특징으로 하는 방법.In an interfacing method between an emulator and a host of a data processing system including a target board, a state machine for controlling a state in which a buffer memory is accessed to enable real-time interface of data to be processed between the emulator and the host. Interfacing using phosphorus. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950042988A 1995-11-22 1995-11-22 Real time interfacing method between emulator and host KR0184454B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950042988A KR0184454B1 (en) 1995-11-22 1995-11-22 Real time interfacing method between emulator and host

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950042988A KR0184454B1 (en) 1995-11-22 1995-11-22 Real time interfacing method between emulator and host

Publications (2)

Publication Number Publication Date
KR970029099A true KR970029099A (en) 1997-06-26
KR0184454B1 KR0184454B1 (en) 1999-05-15

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KR1019950042988A KR0184454B1 (en) 1995-11-22 1995-11-22 Real time interfacing method between emulator and host

Country Status (1)

Country Link
KR (1) KR0184454B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100772841B1 (en) * 2006-07-28 2007-11-02 삼성전자주식회사 Multi-path accessible semiconductor memory device with host interfacing between processors

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100434309B1 (en) * 1998-03-09 2005-05-24 주식회사 하이닉스반도체 Emulator circuit
KR100855587B1 (en) 2007-01-17 2008-09-01 삼성전자주식회사 Multi-path accessible semiconductor memory device having mail box regions and method for mail box access control therefore

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100772841B1 (en) * 2006-07-28 2007-11-02 삼성전자주식회사 Multi-path accessible semiconductor memory device with host interfacing between processors

Also Published As

Publication number Publication date
KR0184454B1 (en) 1999-05-15

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