KR970024703A

KR970024703A - Error Detection Circuit of Serial Data

Info

Publication number: KR970024703A
Application number: KR1019950035057A
Authority: KR
Inventors: 원덕희
Original assignee: 서두칠; 대우전자부품 주식회사
Priority date: 1995-10-12
Filing date: 1995-10-12
Publication date: 1997-05-30

Abstract

본 발명은 시리얼 데이터(serial data)의 에러 검출 회로에 관한 것으로, 주파수를 발진하는 발진기(101), 상기 발진기(101)로부터의 주파수를 분주하는 주파수 분할기(102), 상기 주파수 분할기(102)로부터 분주된 주파수를 받아 펄스의 타이밍을 설정하는 타이밍 제어부(103), 상기 병렬로 입력된 입력 데이터를 받아들여 이를 시리얼로 전송하기 위하여 각각의 데이터를 쉬프트시키며 상기 타이밍 제어부(103)의 타이밍에 따라 데이터를 시리얼로 전송하는 쉬프트 레지스터(104) 및 쉬프트 레지스터(104)로부터 데이터를 받아 이를 인버팅시키는 인버팅부(105)를 포함하는 송신부(100); 및 주파수를 발진하는 발진기(201), 상기 발진기(201)로부터의 주파수를 분주하는 주파수 분할기(202), 펄스의 타이밍을 설정하는 타이밍 제어부(203), 상기 타이밍 제어부(203)의 타이밍에 따라 데이터를 시리얼로 수신하여 이를 필요한 부분에 보내기 위하여 수신된 시리얼 데이터를 병렬 데이터로 변환하여 출력하는 쉬프트 레지스터(204) 및 전송 데이터의 시작부분을 검출하고 인버팅된 데이터와 인버팅되지 않은 데이터를 비교하여 전송도중 발생된 에러를 검출하는 시작 및 에러 검출부(206)를 포함하는 수신부(200)로 구성된다.The present invention relates to an error detection circuit for serial data, comprising: an oscillator 101 for oscillating frequency, a frequency divider 102 for dividing a frequency from the oscillator 101, and a frequency divider 102; A timing controller 103 which receives the divided frequency and sets the timing of the pulse, shifts each data to receive the input data input in parallel and transmit the serial data, and according to the timing of the timing controller 103 A transmission unit 100 including a shift register 104 for transmitting the serial signal and an inverting unit 105 for receiving data from the shift register 104 and inverting the data; And an oscillator 201 for oscillating a frequency, a frequency divider 202 for dividing a frequency from the oscillator 201, a timing controller 203 for setting timing of pulses, and data according to the timing of the timing controller 203. In order to receive the serial data and send it to the required part, the shift register 204 for converting the received serial data into parallel data and outputting the detected data is detected, and the inverted data is compared with the inverted data. It consists of a receiver 200 including a start and error detector 206 for detecting an error generated during transmission.

Description

Error Detection Circuit of Serial Data

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 시리얼 데이터의 에러 검출 회로에 대한 블록도이다.3 is a block diagram of an error detection circuit of serial data according to the present invention.

Claims

An oscillator 101 for oscillating a frequency, a frequency divider 102 for dividing a frequency from the oscillator 101, a timing controller 103 for receiving a frequency divided from the frequency divider 102 and setting a timing of a pulse; From the shift register 104 and the shift register 104 to accept the input data input in parallel and to transfer each data in order to transmit them serially, and to transmit the data serially in accordance with the timing of the timing controller 103 A transmitter 100 including an inverting unit 105 which receives data and inverts it; And an oscillator 201 for oscillating a frequency, a frequency divider 202 for dividing a frequency from the oscillator 201, a timing controller 203 for setting timing of pulses, and data according to the timing of the timing controller 203. In order to receive the serial data and send it to the required part, the shift register 204 for converting the received serial data into parallel data and outputting the detected data is detected, and the inverted data is compared with the inverted data. And a receiving unit (200) including a start pulse for detecting an error generated during transmission and an error detecting unit (206).

2. The error detection circuit of claim 1, wherein inverting data is transmitted after uninverted data.

2. The error detection circuit of serial data according to claim 1, wherein the start pulse and error detection section (206) simultaneously performs start pulse detection and error detection.

※ Note: The disclosure is based on the initial application.