KR970024153A - Layout to reduce cell and core contact area of semiconductor device - Google Patents

Layout to reduce cell and core contact area of semiconductor device Download PDF

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Publication number
KR970024153A
KR970024153A KR1019950037170A KR19950037170A KR970024153A KR 970024153 A KR970024153 A KR 970024153A KR 1019950037170 A KR1019950037170 A KR 1019950037170A KR 19950037170 A KR19950037170 A KR 19950037170A KR 970024153 A KR970024153 A KR 970024153A
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KR
South Korea
Prior art keywords
type
region
well
contact area
layout
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Application number
KR1019950037170A
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Korean (ko)
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KR100189975B1 (en
Inventor
김대용
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950037170A priority Critical patent/KR100189975B1/en
Publication of KR970024153A publication Critical patent/KR970024153A/en
Application granted granted Critical
Publication of KR100189975B1 publication Critical patent/KR100189975B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

반도체 메모리 장치 내의 셀과 상기 셀에 연결되는 코아부분과의 접촉면적을 줄이기 위한 레이아웃방법에 관한 것으로, 셀영역의 트랜지스터 뿐만 아니라 상기 코아영역의 일부 트랜지스터 소자까지 포켓P웰 내에 형성되도록 반도체 메모리 회로를 배치한다.A layout method for reducing the contact area between a cell in a semiconductor memory device and a core portion connected to the cell, wherein the semiconductor memory circuit is formed so that not only transistors in the cell region but also some transistor elements in the core region are formed in the pocket P well. To place.

Description

반도체 장치의 셀과 코아부분 접촉면적을 줄이기 위한 레이아웃Layout to reduce cell and core contact area of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 본 발명에 따른 제1도의 레이아웃도를 나타낸다,4 shows a layout of FIG. 1 according to the invention,

제5도는 제4도의 B-B선에 따른 수직단면도를 나타낸다.5 is a vertical cross-sectional view taken along the line B-B in FIG.

Claims (3)

셀영역과 주변영역을 가지는 반도체 메모리 회로에 있어서, 제1형의 반도체 기판, 상기 반도체 기판 상에 형성된 제2형의 제1웰 영역과, 상기 제2형의 제1웰 영역에 의해 둘러싸인 제1형의 제2웰 영역과, 상기 제2형의 제1웰 영역의 상면에 형성된 주변영역의 제1트랜지스터 소자, 상기 제1형의 웰 영역의 상면에 형성된 상기 주변 영역의 제2트랜지스터 소자, 및 상기 제1웰 영역의 상면에 형성된 상기 셀영역의 트랜지스터를 구비함을 특징으로 하는 반도체 메모리 장치의 레이아웃방법.A semiconductor memory circuit having a cell region and a peripheral region, comprising: a first substrate surrounded by a semiconductor substrate of a first type, a first well region of a second type formed on the semiconductor substrate, and a first well region of the second type; A second well region of the type, a first transistor element in the peripheral region formed on the upper surface of the first well region of the second type, a second transistor element in the peripheral region formed on the upper surface of the well region of the first type, and And a transistor in the cell region formed on the upper surface of the first well region. 제1항에 있어서, 상기 제2형의 제1웰은 N형웰이고 상기 제1형의 제2웰은 P형웰임을 특징으로 하는 반도체 메모리 장치의 레이아웃방법.The method of claim 1, wherein the first well of the second type is an N type well and the second well of the first type is a P type well. 제1항에 있어서, 상기 주변영역의 일부 트랜지스터 소자와 상기 셀영역의 트랜지스터는 N형 트랜지스터이고, 상기 주변영역의 나머지 소자는 P형트랜지스터로 구성됨을 특징으로 하는 반도체 메모리 장치의 레이아웃방법.The method of claim 1, wherein the transistors of the peripheral region and the transistors of the cell region are N-type transistors, and the remaining elements of the peripheral region are P-type transistors. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950037170A 1995-10-25 1995-10-25 Layout for reducing contact size of cell and core part of semiconductor KR100189975B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950037170A KR100189975B1 (en) 1995-10-25 1995-10-25 Layout for reducing contact size of cell and core part of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950037170A KR100189975B1 (en) 1995-10-25 1995-10-25 Layout for reducing contact size of cell and core part of semiconductor

Publications (2)

Publication Number Publication Date
KR970024153A true KR970024153A (en) 1997-05-30
KR100189975B1 KR100189975B1 (en) 1999-06-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950037170A KR100189975B1 (en) 1995-10-25 1995-10-25 Layout for reducing contact size of cell and core part of semiconductor

Country Status (1)

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KR (1) KR100189975B1 (en)

Also Published As

Publication number Publication date
KR100189975B1 (en) 1999-06-01

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