KR970018504A - Duty ratio adjustment circuit - Google Patents

Duty ratio adjustment circuit Download PDF

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Publication number
KR970018504A
KR970018504A KR1019950032960A KR19950032960A KR970018504A KR 970018504 A KR970018504 A KR 970018504A KR 1019950032960 A KR1019950032960 A KR 1019950032960A KR 19950032960 A KR19950032960 A KR 19950032960A KR 970018504 A KR970018504 A KR 970018504A
Authority
KR
South Korea
Prior art keywords
circuit
ratio adjustment
adjustment circuit
duty ratio
present
Prior art date
Application number
KR1019950032960A
Other languages
Korean (ko)
Inventor
주기모
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950032960A priority Critical patent/KR970018504A/en
Publication of KR970018504A publication Critical patent/KR970018504A/en

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Abstract

본 발명은 충격비 조정회로에 관해 게시한다. 종래에는 충격비를 조정하기 위해서 회로구성을 변경해야 하는 단점이 있었으나 본 발명은 신호지연회로 중 지연셀을 추가하거나 삭제함으로써 간단하게 충격비를 조정할 수 있다. 본 발명은 동기회로와 신호지연회로와 복호기(decoder)가 일련으로 접속된 회로로 구성된다.The present invention relates to an impact ratio adjustment circuit. Conventionally, the circuit configuration has to be changed in order to adjust the impact ratio, but the present invention can simply adjust the impact ratio by adding or deleting delay cells in the signal delay circuit. The present invention is composed of a circuit in which a synchronous circuit, a signal delay circuit, and a decoder are connected in series.

Description

충격비(duty ratio) 조정회로Duty ratio adjustment circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 일예에 의한 충격비 조정회로.3 is a shock ratio adjustment circuit according to an embodiment of the present invention.

Claims (2)

동기회로와 신호지연회로와 복호기(decoder)가 일련으로 접속되어 구성된 것을 특징으로 하는 충격비 조정회로.A shock ratio adjustment circuit comprising a synchronization circuit, a signal delay circuit, and a decoder connected in series. 제1항에 있어서, 상기 동기회로는 플립플롭인 것을 특징으로 하는 충격비 조정회로.2. The impact ratio adjustment circuit according to claim 1, wherein the synchronization circuit is a flip flop.
KR1019950032960A 1995-09-29 1995-09-29 Duty ratio adjustment circuit KR970018504A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950032960A KR970018504A (en) 1995-09-29 1995-09-29 Duty ratio adjustment circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950032960A KR970018504A (en) 1995-09-29 1995-09-29 Duty ratio adjustment circuit

Publications (1)

Publication Number Publication Date
KR970018504A true KR970018504A (en) 1997-04-30

Family

ID=66615472

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950032960A KR970018504A (en) 1995-09-29 1995-09-29 Duty ratio adjustment circuit

Country Status (1)

Country Link
KR (1) KR970018504A (en)

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