KR910015120A - Clock Extraction Circuit Using Internal Delay Characteristics of Logic Devices - Google Patents

Clock Extraction Circuit Using Internal Delay Characteristics of Logic Devices Download PDF

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Publication number
KR910015120A
KR910015120A KR1019900000674A KR900000674A KR910015120A KR 910015120 A KR910015120 A KR 910015120A KR 1019900000674 A KR1019900000674 A KR 1019900000674A KR 900000674 A KR900000674 A KR 900000674A KR 910015120 A KR910015120 A KR 910015120A
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KR
South Korea
Prior art keywords
clock extraction
extraction circuit
logic devices
internal delay
delay characteristics
Prior art date
Application number
KR1019900000674A
Other languages
Korean (ko)
Inventor
공비호
Original Assignee
정용문
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정용문, 삼성전자 주식회사 filed Critical 정용문
Priority to KR1019900000674A priority Critical patent/KR910015120A/en
Publication of KR910015120A publication Critical patent/KR910015120A/en

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  • Pulse Circuits (AREA)

Abstract

내용 없음No content

Description

논리소자의 내부지연 특성을 이용한 클럭추출회로Clock Extraction Circuit Using Internal Delay Characteristics of Logic Devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 구성도.2 is a block diagram of the present invention.

Claims (1)

클럭추출수단(2)를 구비한 논리소자의 내부지연 특성을 이용한 클럭추출회로에 있어서, NRZ신호가 입력될때 내부논리 소장의 지연특성을 이용하여 RZ과 유사한 신호를 상기 클럭추출수단(2)로 출력하는 와이어드 오아수단(1)을 구비한 회로.A clock extraction circuit using an internal delay characteristic of a logic element having a clock extraction means (2), wherein when a NRZ signal is input, a signal similar to RZ is transferred to the clock extraction means (2) by using a delay characteristic of an internal logic device. A circuit comprising wired ora means (1) for outputting. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900000674A 1990-01-20 1990-01-20 Clock Extraction Circuit Using Internal Delay Characteristics of Logic Devices KR910015120A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900000674A KR910015120A (en) 1990-01-20 1990-01-20 Clock Extraction Circuit Using Internal Delay Characteristics of Logic Devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900000674A KR910015120A (en) 1990-01-20 1990-01-20 Clock Extraction Circuit Using Internal Delay Characteristics of Logic Devices

Publications (1)

Publication Number Publication Date
KR910015120A true KR910015120A (en) 1991-08-31

Family

ID=67468232

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900000674A KR910015120A (en) 1990-01-20 1990-01-20 Clock Extraction Circuit Using Internal Delay Characteristics of Logic Devices

Country Status (1)

Country Link
KR (1) KR910015120A (en)

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