KR970018412A - Method for manufacturing metal wiring of semiconductor device - Google Patents

Method for manufacturing metal wiring of semiconductor device Download PDF

Info

Publication number
KR970018412A
KR970018412A KR1019950032094A KR19950032094A KR970018412A KR 970018412 A KR970018412 A KR 970018412A KR 1019950032094 A KR1019950032094 A KR 1019950032094A KR 19950032094 A KR19950032094 A KR 19950032094A KR 970018412 A KR970018412 A KR 970018412A
Authority
KR
South Korea
Prior art keywords
metal layer
pattern
metal
insulating film
forming
Prior art date
Application number
KR1019950032094A
Other languages
Korean (ko)
Other versions
KR100214261B1 (en
Inventor
배상만
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950032094A priority Critical patent/KR100214261B1/en
Publication of KR970018412A publication Critical patent/KR970018412A/en
Application granted granted Critical
Publication of KR100214261B1 publication Critical patent/KR100214261B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체소자의 금속배선 제조방법에 관한 것으로서, 금속배선용 노광마스크를 패턴이 하나 걸려 하나씩 형성되어 있는 두장으로 분리 제작하여 패턴간의 스테이스가 충분히 크게한 후, 절연막상에 제1금속층 패턴을 하나의 노광마스크를 사용하여 형성하여 패턴간에 충분한 스페이스를 갖도록하고, 상기 제1금속층 패턴 사이의 절연막상에 다른 노광마스크를 사용하여 다시 충분한 스페이스를 갖는 제2금속층 패턴을 형성하여 제1 및 제2금속층 패턴으로 구성되는 금속배선을 형성하였으므로, 두 번째 걸친 사진 식각 공정이 진행되므로 매 공정마다에서는 패턴간 스페이스가 충분히 넓어 지므로 셀영역과 주변회로 영역간의 단차에 의해 발생되는 패턴간 브릿지가 방지되고, 서로 다른 재질의 두금속층으로 비저항을 조절하여 형성할 수 있으므로 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a metal wiring of a semiconductor device, wherein the exposure mask for metal wiring is separated into two sheets formed by hanging a pattern one by one so that the state between the patterns is sufficiently large, and then a first metal layer pattern is formed on the insulating film. And a second metal layer pattern having sufficient space on the insulating film between the first metal layer patterns by using another exposure mask again to form a second metal layer pattern having sufficient space. Since the metal wiring formed of the pattern is formed, the second photolithography process is performed, so that the space between the patterns is sufficiently wide in every process, thereby preventing the inter-pattern bridge caused by the step between the cell region and the peripheral circuit region. Bimetallic layer of different materials can be formed by adjusting the specific resistance Therefore, the process yield and the reliability of device operation can be improved.

Description

반도체소자의 금속배선 제조방법Method for manufacturing metal wiring of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 제1도의 공정에 의해 금속배선이 형성되어 있는 반도체소자의 레이아웃도.2 is a layout diagram of a semiconductor device in which metal wiring is formed by the process of FIG.

Claims (5)

소정구조의 반도체기판상에 절연막을 형성하는 공정과, 상기 절연막상에 제1금속층을 형성하는 공정과, 상기 제1금속층을 감광막패턴을 이용하여 사진 식각하되, 금속배선으로 예정되어있는 부분에 대하여 하나 걸려 하나씩 마다 패턴을 형성하여 스페이스가 형성하고자 하는 금속배선에 비해 증가되도록 형성하는 공정과, 상기 구조의 전표면에 제2금속층을 형성하는 공정과, 상기 제1금속층 패턴 사이에서 금속패턴으로 예정되어있는 부분 상에 상기 제1금속층 패턴과는 단선된 제2금속층 패턴을 형성하는 공정을 구비하는 반도체소자의 금속배선 제조방법.Forming an insulating film on a semiconductor substrate having a predetermined structure; forming a first metal layer on the insulating film; and etching a portion of the first metal layer using a photosensitive film pattern, wherein the portion is scheduled for metal wiring. Forming a pattern every one by one so that the space is increased compared to the metal wiring to be formed; forming a second metal layer on the entire surface of the structure; and a metal pattern between the first metal layer pattern. And forming a second metal layer pattern disconnected from the first metal layer pattern on a portion thereof. 제1항에 있어서, 상기 제1 및 제2금속층을 각각 W 계열 금속층 합금과, A1 계열 금속층 합금으로 형성하고 후속정을 진향하는 것을 특징으로 하는 반도체소자의 금속배선 제조방법.The method of claim 1, wherein the first and second metal layers are formed of a W-based metal layer alloy and an A1-based metal layer alloy, respectively, and follow-up. 제2항에 있어서, 상기 제1금속층을 W 계열 금속층으로 사용하는 경우 절연막상에 베리어메탈을 형성하고 후속정을 진향하는 것을 특징으로 하는 반도체소자의 금속배선 제조방법.The method of claim 2, wherein when the first metal layer is used as a W-based metal layer, a barrier metal is formed on the insulating film, and a subsequent crystal is advanced. 제2항에 있어서, 상기 제1 및 제2금속층을 W계열 합금과 A1 계열 금속층합금으로 형성하는 경우 W 계열 합금을 1000∼2000Å 정도 두껍게 형성하거나, 선폭을 A1계열 합금 보다 0.05∼0.1㎛ 정도 크게 형성하는 것을 특징으로 하는 반도체소자의 금속배선 제조방법.3. The method of claim 2, wherein when the first and second metal layers are formed of a W series alloy and an A1 series metal layer alloy, the W series alloy is formed to have a thickness of about 1000 to 2000 microns, or the line width is about 0.05 to 0.1 µm larger than that of the A1 series alloy. Metal wire manufacturing method of a semiconductor device, characterized in that it is formed. 제1항에 있어서, 상기 제1금속층 패턴 형성후, 절연막을 500∼2000Å 두께로 형형성하고 후속 공정을 진행하여 제2금속층 식각 공정시 제1금속층 패턴이 손상되는 것을 방지하는 것을 특징으로 하는 반도체소자의 금속배선 제조방법.The semiconductor of claim 1, wherein after forming the first metal layer pattern, an insulating film is formed to a thickness of 500 to 2000 Å and a subsequent process is performed to prevent the first metal layer pattern from being damaged during the second metal layer etching process. Method for manufacturing metal wiring of device.
KR1019950032094A 1995-09-27 1995-09-27 Method for forming metal wiring in semiconductor device KR100214261B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950032094A KR100214261B1 (en) 1995-09-27 1995-09-27 Method for forming metal wiring in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950032094A KR100214261B1 (en) 1995-09-27 1995-09-27 Method for forming metal wiring in semiconductor device

Publications (2)

Publication Number Publication Date
KR970018412A true KR970018412A (en) 1997-04-30
KR100214261B1 KR100214261B1 (en) 1999-08-02

Family

ID=19427985

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950032094A KR100214261B1 (en) 1995-09-27 1995-09-27 Method for forming metal wiring in semiconductor device

Country Status (1)

Country Link
KR (1) KR100214261B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100298239B1 (en) * 1997-09-19 2001-09-06 니시무로 타이죠 Array substrate of display device, lcd comprising an array substrate, and method of manufacturing an array substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100298239B1 (en) * 1997-09-19 2001-09-06 니시무로 타이죠 Array substrate of display device, lcd comprising an array substrate, and method of manufacturing an array substrate

Also Published As

Publication number Publication date
KR100214261B1 (en) 1999-08-02

Similar Documents

Publication Publication Date Title
JPH08160590A (en) Formation of pattern, production of reticle and semiconductor device
US6027859A (en) Semiconductor substrate having extended scribe line test structure and method of fabrication thereof
KR970018412A (en) Method for manufacturing metal wiring of semiconductor device
KR970051945A (en) Manufacturing Method of Semiconductor Device
US5902717A (en) Method of fabricating semiconductor device using half-tone phase shift mask
JP2796068B2 (en) Method of forming photosensitive film pattern
JP2666383B2 (en) Semiconductor device
JP2830636B2 (en) Method for manufacturing semiconductor device
KR100329605B1 (en) Method for manufacturing metal wiring in semiconductor device
KR100359250B1 (en) Method for reporting overlay margin using assistant thin film
KR970008417A (en) How to Form Flat Conductor Patterns
KR960026398A (en) Method for manufacturing metal wiring of semiconductor device
JPS62171142A (en) Wiring formation
JPH0245909A (en) Manufacture of semiconductor device
KR950021097A (en) Fine contact formation method of highly integrated semiconductor device
KR19980066697A (en) Manufacturing Method of Semiconductor Device
JPH03123059A (en) Semiconductor device
JPS6270594A (en) Selective plating method
KR950025937A (en) Pad Formation Method of Semiconductor Device
JPS62171194A (en) Matrix wiring board
KR950025874A (en) Method for manufacturing gate electrode of semiconductor device
JPH0567608A (en) Wiring pattern in semiconductor device
KR960019517A (en) Method for manufacturing contact hole of semiconductor device
JPH06102658A (en) Photoresist pattern forming method and exposure mask
JPH03262115A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090427

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee