KR970017696A - Test method of semiconductor memory device - Google Patents
Test method of semiconductor memory device Download PDFInfo
- Publication number
- KR970017696A KR970017696A KR1019950033270A KR19950033270A KR970017696A KR 970017696 A KR970017696 A KR 970017696A KR 1019950033270 A KR1019950033270 A KR 1019950033270A KR 19950033270 A KR19950033270 A KR 19950033270A KR 970017696 A KR970017696 A KR 970017696A
- Authority
- KR
- South Korea
- Prior art keywords
- input
- address strobe
- column address
- cell array
- memory device
- Prior art date
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
본 발명은 반도체 메모리 장치의 테스트 방법에 관한 것으로서, 특히 복수의 셀어레이 블럭들, 주변회로부, 복수의 입출력 패드들을 가지는 반도체 메모리 장치에 있어서, 복수의 입출력 패드들 중 적어도 하나 이상의 입출력모드를 통하여 테스트 모드하의 컬럼 어드레스 스트로브 신호를 입력하는 단계; 입력된 컬럼 어드레스 스트로브 신호를 서로 지연시간이 다르게 셀어레이 블럭들과 동수의 테스트 컬럼 어드레스 스트로브 신호로 발생하는 단계; 및 각 테스트 컬럼 어드레스 스트로브 신호들에 응답하여 각 셀어레이 블럭으로부터 데이타를 출력하는 단계를 구비하여, 칩 내부적으로 동시에 서로 다른 복수의 타이밍 조건에서의 동작상태를 테스팅할 수 있는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method for a semiconductor memory device, and more particularly, to a semiconductor memory device having a plurality of cell array blocks, a peripheral circuit unit, and a plurality of input / output pads, wherein the test is performed through at least one input / output mode among the plurality of input / output pads. Inputting a column address strobe signal under mode; Generating the input column address strobe signal as a test column address strobe signal equal to the cell array blocks having different delay times; And outputting data from each cell array block in response to the respective test column address strobe signals, so that an operation state under a plurality of different timing conditions can be simultaneously tested internally in the chip.
따라서, 본 발명에서는 보다 다양한 타이밍조건에서의 칩테스팅을 보다 짧은 시간에 할 수 있다.Therefore, in the present invention, chip testing in more various timing conditions can be performed in a shorter time.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제4도 내지 제7도는 본 발명에 의한 반도체 메모리 장치의 테스트 개념도.4 to 7 are test conceptual views of a semiconductor memory device according to the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950033270A KR970017696A (en) | 1995-09-30 | 1995-09-30 | Test method of semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950033270A KR970017696A (en) | 1995-09-30 | 1995-09-30 | Test method of semiconductor memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970017696A true KR970017696A (en) | 1997-04-30 |
Family
ID=66583424
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950033270A KR970017696A (en) | 1995-09-30 | 1995-09-30 | Test method of semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970017696A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100379532B1 (en) * | 2001-04-18 | 2003-04-10 | 주식회사 하이닉스반도체 | Circuit for controlling column |
-
1995
- 1995-09-30 KR KR1019950033270A patent/KR970017696A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100379532B1 (en) * | 2001-04-18 | 2003-04-10 | 주식회사 하이닉스반도체 | Circuit for controlling column |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR870002582A (en) | Semiconductor Memory with Test Pattern Generation Circuit | |
KR850004684A (en) | Semiconductor memory | |
KR960008544A (en) | Method and apparatus for selecting multiple memory banks | |
KR890017706A (en) | Dynamic Semiconductor Memory | |
DE69628196D1 (en) | DEVICE AND METHOD FOR SWITCHING ON A FUNCTION IN A MEMORY MODULE | |
KR960042765A (en) | Memory Cell Test Control Circuit and Method of Semiconductor Memory Device | |
KR970051455A (en) | Semiconductor memory device having redundant cell test control circuit | |
KR930017028A (en) | Semiconductor memory device having a plurality of RAS signals | |
KR940002865A (en) | Burn-in enable circuit and burn-in test method of semiconductor memory device | |
KR970017694A (en) | High speed test circuit of semiconductor memory device | |
KR950015399A (en) | Semiconductor memory device for input and output of bit unit data | |
KR900019050A (en) | Semiconductor integrated circuit device | |
KR970023464A (en) | Semiconductor memory with test circuit | |
KR910001744A (en) | Semiconductor memory | |
KR970076884A (en) | Multi-bit test circuit of semiconductor memory device and test method thereof | |
KR100265758B1 (en) | Merged dq circuit of semiconductor device and merged dq method thereof | |
KR100217267B1 (en) | Memory device having switching circuit for control internal address | |
KR970051456A (en) | Semiconductor memory device can reduce the number of DQ channels | |
KR970030584A (en) | Semiconductor memory | |
KR980003618A (en) | Memory test device | |
KR970017696A (en) | Test method of semiconductor memory device | |
JPH1166899A (en) | Memory test circuit | |
KR950006876A (en) | Roll call circuit | |
JPS61261895A (en) | Semiconductor memory device | |
KR970060223A (en) | Semiconductor memory device and control method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WITN | Withdrawal due to no request for examination |