KR970017696A - Test method of semiconductor memory device - Google Patents

Test method of semiconductor memory device Download PDF

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Publication number
KR970017696A
KR970017696A KR1019950033270A KR19950033270A KR970017696A KR 970017696 A KR970017696 A KR 970017696A KR 1019950033270 A KR1019950033270 A KR 1019950033270A KR 19950033270 A KR19950033270 A KR 19950033270A KR 970017696 A KR970017696 A KR 970017696A
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KR
South Korea
Prior art keywords
input
address strobe
column address
cell array
memory device
Prior art date
Application number
KR1019950033270A
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Korean (ko)
Inventor
강경우
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950033270A priority Critical patent/KR970017696A/en
Publication of KR970017696A publication Critical patent/KR970017696A/en

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

본 발명은 반도체 메모리 장치의 테스트 방법에 관한 것으로서, 특히 복수의 셀어레이 블럭들, 주변회로부, 복수의 입출력 패드들을 가지는 반도체 메모리 장치에 있어서, 복수의 입출력 패드들 중 적어도 하나 이상의 입출력모드를 통하여 테스트 모드하의 컬럼 어드레스 스트로브 신호를 입력하는 단계; 입력된 컬럼 어드레스 스트로브 신호를 서로 지연시간이 다르게 셀어레이 블럭들과 동수의 테스트 컬럼 어드레스 스트로브 신호로 발생하는 단계; 및 각 테스트 컬럼 어드레스 스트로브 신호들에 응답하여 각 셀어레이 블럭으로부터 데이타를 출력하는 단계를 구비하여, 칩 내부적으로 동시에 서로 다른 복수의 타이밍 조건에서의 동작상태를 테스팅할 수 있는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method for a semiconductor memory device, and more particularly, to a semiconductor memory device having a plurality of cell array blocks, a peripheral circuit unit, and a plurality of input / output pads, wherein the test is performed through at least one input / output mode among the plurality of input / output pads. Inputting a column address strobe signal under mode; Generating the input column address strobe signal as a test column address strobe signal equal to the cell array blocks having different delay times; And outputting data from each cell array block in response to the respective test column address strobe signals, so that an operation state under a plurality of different timing conditions can be simultaneously tested internally in the chip.

따라서, 본 발명에서는 보다 다양한 타이밍조건에서의 칩테스팅을 보다 짧은 시간에 할 수 있다.Therefore, in the present invention, chip testing in more various timing conditions can be performed in a shorter time.

Description

반도체 메모리 장치의 테스트 방법Test method of semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도 내지 제7도는 본 발명에 의한 반도체 메모리 장치의 테스트 개념도.4 to 7 are test conceptual views of a semiconductor memory device according to the present invention.

Claims (1)

복수의 셀어레이 블럭들, 주변회로부, 복수의 입출력 패드들을 가지는 반도체 메모리 장치에 있어서, 복수의 입출력 패드들 중 적어도 하나 이상의 입출력모드를 통하여 테스트 모드하의 컬럼 어드레스 스트로브 신호를 입력하는 단계, 입력된 컬럼 어드레스 스트로브 신호를 서로 지연시간이 다르게 셀어레이 블럭들과 등수의 테스트 컬럼 어드레스 스트로브 신호로 발생하는 단계, 및 상기 각 테스트 컬럼 어드레스 스트로브 신호들에 응답하여 각 겔어레이 블럭으로부터 데이타를 출력하는 단계를 구비하여, 칩 내부적으로 동시에 서로 다른 복수의 타이밍 조건에서의 동작상태를 테스팅할 수 있는 것을 특징으로 하는 반도체 메모리 장치의 테스트 방법.A semiconductor memory device having a plurality of cell array blocks, a peripheral circuit unit, and a plurality of input / output pads, the method comprising: inputting a column address strobe signal under a test mode through at least one input / output mode of the plurality of input / output pads, the input column Generating an address strobe signal as a cell array block and an equal number of test column address strobe signals having different delay times, and outputting data from each gel array block in response to the respective test column address strobe signals; And testing the operating states under a plurality of different timing conditions at the same time internally in the chip. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950033270A 1995-09-30 1995-09-30 Test method of semiconductor memory device KR970017696A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950033270A KR970017696A (en) 1995-09-30 1995-09-30 Test method of semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950033270A KR970017696A (en) 1995-09-30 1995-09-30 Test method of semiconductor memory device

Publications (1)

Publication Number Publication Date
KR970017696A true KR970017696A (en) 1997-04-30

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Application Number Title Priority Date Filing Date
KR1019950033270A KR970017696A (en) 1995-09-30 1995-09-30 Test method of semiconductor memory device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100379532B1 (en) * 2001-04-18 2003-04-10 주식회사 하이닉스반도체 Circuit for controlling column

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100379532B1 (en) * 2001-04-18 2003-04-10 주식회사 하이닉스반도체 Circuit for controlling column

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