KR970017633A - Bit Line Equalization Control Circuit of Semiconductor Memory Device - Google Patents

Bit Line Equalization Control Circuit of Semiconductor Memory Device Download PDF

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Publication number
KR970017633A
KR970017633A KR1019950029570A KR19950029570A KR970017633A KR 970017633 A KR970017633 A KR 970017633A KR 1019950029570 A KR1019950029570 A KR 1019950029570A KR 19950029570 A KR19950029570 A KR 19950029570A KR 970017633 A KR970017633 A KR 970017633A
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South Korea
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voltage
equalization control
bit line
signal
memory device
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KR1019950029570A
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Korean (ko)
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KR0164392B1 (en
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이규찬
문병식
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김광호
삼성전자 주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

다이내믹 랜덤 억세스 메모리장치Dynamic Random Access Memory Device

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

다이내믹 랜덤 억세스 메모리장치에서 등화제어신호를 두 레벨의 전압으로 발생시켜 등화 속도를 개선하여 사이클 시간을 줄임Dynamic Random Access Memory Device Generates Equalization Control Signals at Two Levels of Voltage to Improve Equalization Speed and Reduce Cycle Time

3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention

비트라인에 연결되며 등화제어신호에 의해 상기 비트라인을 프리차지 및 등화하는 수단을 구비하는 반도체 메모리장치의 등화제어회로가, 등화 제어신호를 발생하는 수단과, 제1전압과 상기 등화제어신호 발생수단에 연결되며, 프리차지주기의 전반부에 발생되는 제1신호에 의해 스위칭되어 상기 제1전압을 공급하는 수단과, 제2전압과 상기 등화제어신호 발생수단에 연결되며, 상기 프리차지주기의 후반부에 발생되는 제2신호에 의해 스위칭되어 상기 제2전압을 공급하는 수단으로 구성되어, 상기 등화제어신호가 프리차지 주기의 전반부에 제1전압으로 발생되고 후반부에서 제2전압으로 발생된다.An equalization control circuit of a semiconductor memory device, connected to a bit line and having means for precharging and equalizing the bit line by an equalization control signal, includes: means for generating an equalization control signal, and generating a first voltage and the equalization control signal; Means for supplying the first voltage, switched by a first signal generated in the first half of the precharge period, and connected to a second voltage and the equalization control signal generating means, the second half of the precharge period Means for supplying the second voltage by switching by a second signal generated at the second signal, wherein the equalization control signal is generated as a first voltage in the first half of the precharge period and as a second voltage in the second half.

4. 발명의 중요한 용도4. Important uses of the invention

다이내믹 랜덤 억세스 메모리장치에서 등화제어신호를 두 레벨의 전압으로 발생하므로서, 프리차지시 빠르게 비트라인을 프리차지 및 등화시켜 메모리셀의 정보 억세스를 안정하게 수행함.In the dynamic random access memory device, the equalization control signal is generated at two levels of voltage, thereby precharging and equalizing the bit line quickly during precharging, thereby stably accessing information of the memory cell.

Description

반도체 메모리장치의 비트라인 등화제어회로Bit Line Equalization Control Circuit of Semiconductor Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명에 따라 등화제어신호를 발생하는 제1실시예의 구성을 도시하는 도면,4 is a diagram showing a configuration of a first embodiment for generating an equalization control signal in accordance with the present invention;

제5도는 본 발명에 따라 등화제어신호를 발생하는 제2실시예의 구성을 도시하는 도면.5 is a diagram showing a configuration of a second embodiment for generating an equalization control signal in accordance with the present invention.

Claims (7)

비트라인에 연결되며 등화제어신호에 의해 상기 비트라인을 프리차지 및 등화하는 수단을 가지는 반도체 메모리장치에 있어서, 등화제어신호를 발생하는 수단과, 제1전압과 상기 등화제어신호 발생수단에 연결되며, 프리차지주기의 전반부에 발생되는 제1신호에 의해 스위칭되어 상기 제1전압을 공급하는 수단과, 제2전압과 상기 등화제어신호 발생수단에 연결되며, 상기 프리차지주기의 후반부에 발생되는 제2신호에 의해 스위칭되어 상기 제2전압을 공급하는 수단을 구비하여, 상기 등화제어신호가 프리차지 주기의 전반부에 제1전압으로 발생되고 후반부에서 제2전압으로 발생되는 것을 특징으로 하는 반도체 메모리장치의 비트라인 등화제어회로.A semiconductor memory device having means for precharging and equalizing said bit line by an equalization control signal, said semiconductor memory device comprising: means for generating an equalization control signal, and a first voltage and said equalization control signal generating means; And means for supplying the first voltage, connected to the second voltage and the equalization control signal generating means, switched by a first signal generated in the first half of the precharge period, and being generated in the second half of the precharge period. Means for switching by two signals to supply the second voltage, wherein the equalization control signal is generated as a first voltage in the first half of the precharge period and as a second voltage in the second half; Bit line equalization control circuit. 제1항에 있어서, 상기 제1전압이 전원전압이고 상기 제2전원전압이 전원전압 보다 높은 레벨의 전압인 것을 특징으로하는 반도체 메모리장치의 비트라인 등화제어회로.2. The bit line equalization control circuit of claim 1, wherein the first voltage is a power supply voltage and the second power supply voltage is a voltage higher than the power supply voltage. 비트라인에 연결되며 등화제어신호에 의해 상기 비트라인을 프리차지 등화하는 수단을 가지는 반도체 메모리장치에 있어서, 출력노드와, 상기 출력노드에 연결되며 로우 어드레스 신호를 반전 지연하여 등화제어신호를 발생하는 수단과, 상기 로우 어드레스 신호와 마스터클럭을 수신하여 프리차지 주기의 전반부에서 제1논리 신호를 발생하고 상기 프리차지 주기의 후반부에서 제2논리신호를 발생하는 수단과, 제1전압과 상기 등화제어신호를 발생하는 수단 사이에 연결되며 제어단이 상기 신호발생수단에 연결되어 상기 제1논리신호 발생시 스위칭되어 상기 등화제어신호 발생수단에 제1전압을 공급하는 제1스위칭수단과, 제2전압과 상기 출력노드 사이에 연결되며 제어단이 상기 신호발생수단에 연결되어 상기 제2논리신호 발생시 스위칭되어 상기 출력노드에 제2전압을 공급하는 제2스위칭수단을 구비하여, 상기 등화제어신호가 프리차지 주기의 전반부에 제1전압으로 발생되고 후반부에서 제2전압으로 발생되는 것을 특징으로 하는 반도체 메모리장치의 비트라인 등화제어회로.A semiconductor memory device connected to a bit line and having means for precharging equalization of the bit line by an equalization control signal, the semiconductor memory device comprising: an output node, connected to the output node, and inversely delaying a row address signal to generate an equalization control signal. Means for receiving the row address signal and the master clock to generate a first logic signal in the first half of a precharge period and a second logic signal in the second half of the precharge period, a first voltage and the equalization control. First switching means connected between the means for generating a signal and a control terminal connected to the signal generating means to switch when the first logical signal is generated to supply a first voltage to the equalization control signal generating means, and a second voltage and Connected between the output nodes and a control terminal connected to the signal generating means to switch when the second logical signal is generated. And a second switching means for supplying a second voltage to an output node, wherein the equalization control signal is generated as a first voltage in the first half of the precharge period and as a second voltage in the second half. Bit line equalization control circuit. 제3항에 있어서, 상기 제1전압이 전원전압이고 상기 제2전원전압이 전원전압 보다 높은 레벨의 전압인 것을 특징으로하는 반도체 메모리장치의 비트라인 등화제어회로.4. The bit line equalization control circuit of claim 3, wherein the first voltage is a power supply voltage and the second power supply voltage is a voltage higher than the power supply voltage. 제4항에 있어서, 상기 마스터클럭이 로우 스트로브 어드레스의 반전된 신호인 것을 특징으로 하는 반도체 메모리장치의 비트라인 등화제어회로.5. The bit line equalization control circuit of claim 4, wherein the master clock is an inverted signal having a low strobe address. 제5항에 있어서, 상기 제2스위칭수단이 피모오스트랜지스터인 것을 특징으로 하는 반도체 메모리장치의 비트라인 등화제어회로.6. The bit line equalization control circuit of a semiconductor memory device according to claim 5, wherein said second switching means is a PIO transistor. 제5항에 있어서, 상기 제2스위칭수단이 엔모오스트랜지스터인 것을 특징으로 하는 반도체 메모리장치의 비트라인 등화제어회로.6. The bit line equalization control circuit of a semiconductor memory device according to claim 5, wherein said second switching means is an enMOS transistor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950029570A 1995-09-11 1995-09-11 Bit line equalization control circuit for semiconductor memory device KR0164392B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100486239B1 (en) * 1998-09-02 2005-07-07 삼성전자주식회사 Semiconductor memory device with improved equalization speed

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100486239B1 (en) * 1998-09-02 2005-07-07 삼성전자주식회사 Semiconductor memory device with improved equalization speed

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