KR970015487U - 무조정 전압제어발진기를 가진 위상제어루프회로 - Google Patents
무조정 전압제어발진기를 가진 위상제어루프회로Info
- Publication number
- KR970015487U KR970015487U KR2019950027140U KR19950027140U KR970015487U KR 970015487 U KR970015487 U KR 970015487U KR 2019950027140 U KR2019950027140 U KR 2019950027140U KR 19950027140 U KR19950027140 U KR 19950027140U KR 970015487 U KR970015487 U KR 970015487U
- Authority
- KR
- South Korea
- Prior art keywords
- loop circuit
- unregulated voltage
- voltage control
- control loop
- oscillator
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
- H03L7/189—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop comprising a D/A converter for generating a coarse tuning voltage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019950027140U KR200157538Y1 (ko) | 1995-09-30 | 1995-09-30 | 무조정 전압제어발진기를 가진 위상제어루프회로 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019950027140U KR200157538Y1 (ko) | 1995-09-30 | 1995-09-30 | 무조정 전압제어발진기를 가진 위상제어루프회로 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970015487U true KR970015487U (ko) | 1997-04-28 |
| KR200157538Y1 KR200157538Y1 (ko) | 1999-09-15 |
Family
ID=19424884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019950027140U KR200157538Y1 (ko) | 1995-09-30 | 1995-09-30 | 무조정 전압제어발진기를 가진 위상제어루프회로 |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR200157538Y1 (ko) |
-
1995
- 1995-09-30 KR KR2019950027140U patent/KR200157538Y1/ko not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR200157538Y1 (ko) | 1999-09-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| REGI | Registration of establishment | ||
| FPAY | Annual fee payment |
Payment date: 20080529 Year of fee payment: 10 |
|
| LAPS | Lapse due to unpaid annual fee |