KR970013966A - ATM Selector - Google Patents

ATM Selector Download PDF

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Publication number
KR970013966A
KR970013966A KR1019950023951A KR19950023951A KR970013966A KR 970013966 A KR970013966 A KR 970013966A KR 1019950023951 A KR1019950023951 A KR 1019950023951A KR 19950023951 A KR19950023951 A KR 19950023951A KR 970013966 A KR970013966 A KR 970013966A
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KR
South Korea
Prior art keywords
atm
selector
cell
header
port
Prior art date
Application number
KR1019950023951A
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Korean (ko)
Other versions
KR0161745B1 (en
Inventor
권재철
정학진
Original Assignee
이준
한국전기통신연구소
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이준, 한국전기통신연구소 filed Critical 이준
Priority to KR1019950023951A priority Critical patent/KR0161745B1/en
Publication of KR970013966A publication Critical patent/KR970013966A/en
Application granted granted Critical
Publication of KR0161745B1 publication Critical patent/KR0161745B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H04L49/1553—Interconnection of ATM switching modules, e.g. ATM switching fabrics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/32—Flow control; Congestion control by discarding or delaying data units, e.g. packets or frames
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5665—Interaction of ATM with other protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

본 발명은 B-ISDN 단말을 망에 정합시키기 위해 필요한 장치인 ATM 정합 보드에서, 수신측의 ATM 계층 및 물리계층 기능의 일부를 처리하기 위해 Bt8222 칩을 사용하고, ATM 계층 기능의 일부 및 ATM 적응 계층으로서 AAL-3/4 또는 AAL-5 기능을 국부 프로세서로 처리하는 경우, Bt8222 수신 포트로 출력되는 ATM 셀 중 국부 프로세서가 처리해야 하는 ATM 셀의 양을 하드웨어적으로 경감시킴으로써 국부 프로세서의 처리 능력을 향상시키고 다수의 ATM 연결을 동시에 설정 가능하게 해주는 장치인 ATM 셀 셀렉터에 관한 것이다. 본 발명은 셀렉터 제어기와 두개의 1셀 버퍼로 구성되며, 셀렉터 제어기는 다시 포트헤더 레지스터부, 수신헤더레지스터부, 헤더비교기, 버퍼제어신호발생기 및 버퍼입출력제어기로 구성되어 본 발명의 핵심 기능을 수행한다.The present invention uses a Bt8222 chip to process a part of the ATM layer and physical layer functions of a receiving side in an ATM matching board, which is a device necessary for matching a B-ISDN terminal to a network, and part of the ATM layer function and ATM adaptation. When processing AAL-3 / 4 or AAL-5 functions as a local processor as a layer, the local processor's processing power by hardwarely reducing the amount of ATM cells that the local processor must handle among the ATM cells output to the Bt8222 receiving port. The present invention relates to an ATM cell selector, which is a device that improves performance and allows multiple ATM connections to be established simultaneously. The present invention is composed of a selector controller and two 1-cell buffers. The selector controller is composed of a port header register part, a receive header register part, a header comparator, a buffer control signal generator, and a buffer input / output controller to perform the core functions of the present invention. do.

Description

에이티엠(ATM) 셀 셀렉터ATM Selector

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 ATM 셀 셀렉터의 기본 구성을 도시한 블럭도.2 is a block diagram showing the basic configuration of an ATM cell selector of the present invention.

제3도는 제2도에 도시된 ATM 셀 셀렉터 제어기의 세부 구조를 도시한 블럭도.3 is a block diagram showing the detailed structure of the ATM cell selector controller shown in FIG.

Claims (3)

4개의 수신 포트를 가지고 있는 Bt8222 칩과 국부 프로세서를 사용하여 ATM프로토콜을 처리하는 ATM 정합장치에 있어서, 상기 ATM 셀 셀렉터의 주된 기능을 제어하기 위한 셀렉터 제어기와, 상기 Bt8222 칩의 3번 포트로부터 출력되는 하나의 셀을 임시 저장해 두기 위한 2개의 1셀 버퍼를 구비하는 것을 특징으로 하는 ATM 셀 셀렉터.An ATM matching device for processing an ATM protocol using a Bt8222 chip having four receiving ports and a local processor, comprising: a selector controller for controlling the main functions of the ATM selector, and an output from port 3 of the Bt8222 chip And an ATM cell selector for temporarily storing one cell to be used. 제 1 항에 있어서, 상기 셀렉터 제어기는, 상기 국부 프로세서로부터 두개의 포트헤더레지스터 값중 VPI/VCI값만을 저장해두는 포트헤더레지스터단과, 상기 Bt8222의 3번 포트로부터 출력되는 셀의 헤더 4바이트 중 VPI/VCI 값만을 저장해두는 수신헤더레지스터단과, 상기 수신헤더레지스터단의 값을 두개의 포트헤더레지스터단 값과 동시에 비교하여 비교 결과를 출력하는 헤더비교기와, 상기 비교 결과에 따라 1셀 버퍼의 내용을 폐기하거나 다음 단의 FIFO로 보내주는 신호를 생성하는 버퍼제어신호발생기와, 상기 1셀 버퍼의 데이터 입출력 및 다음단의 FIFO 입력을 제어하는 버퍼입출력제어기로 구성된 것을 특징으로 하는 ATM 셀 셀렉터.4. The selector controller of claim 1, wherein the selector controller comprises: a port header register stage storing only VPI / VCI values of two port header register values from the local processor; and VPI / of header 4 bytes of a cell output from port 3 of the Bt8222. A header comparator that stores only VCI values, a header comparator that compares the values of the received header registers with the values of two port headers, and outputs a comparison result; and discards the contents of the one-cell buffer according to the comparison result. Or a buffer control signal generator for generating a signal to be sent to the next stage FIFO, and a buffer input / output controller for controlling the data input / output of the one-cell buffer and the next stage FIFO input. 제 1 항에 있어서 상기 두개의 1셀 버퍼부를 사용하여 ATM 셀의 입/출력을 동시에 처리하는 것을 특징으로 하는 ATM 셀 셀렉터.The ATM cell selector of claim 1, wherein the input / output of an ATM cell is simultaneously processed using the two one-cell buffer units. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950023951A 1995-08-03 1995-08-03 Atm selector KR0161745B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950023951A KR0161745B1 (en) 1995-08-03 1995-08-03 Atm selector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950023951A KR0161745B1 (en) 1995-08-03 1995-08-03 Atm selector

Publications (2)

Publication Number Publication Date
KR970013966A true KR970013966A (en) 1997-03-29
KR0161745B1 KR0161745B1 (en) 1998-12-01

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