KR0123228B1 - A circuit for generating in aal interrupt of atm system - Google Patents

Abstract

In a device interfacing an ALL layer of an ATM communication method with a higher layer by means of an interrupt, an interrupt processing device of the ATM communication method includes: an ALL3/4 assembly complete signal generating unit (10) inputting a segment type (ST) signal and a complete signal to generate an ALL3/4 assembly complete signal; an AAL5 assembly complete signal generating unit (20) inputting a final cell (m) signal and a complete signal to generate an AAL5 assembly complete signal; an AAL3/4 assembly complete signal storing unit (30) for storing an output of the ALL3/4 assembly complete signal generating unit (10) to transmit it to the higher layer; an ALL5 assembly complete signal storing unit (40) for storing an output of the ALL5 assembly complete signal generating unit 20 to transmit it to the upper layer; an interrupt signal generating unit (50) generating an interrupt signal INT, if the AAL3/4 assembly complete signal, or, if the AAL5 assembly complete signal is input; an address decoder (60) enabling the AAL3/4 assembly complete signal storing unit (30) and the AAL5 assembly complete signal storing unit (40), if a given address is input; and a host computer(2) outputting a given address to read data of the AAL3/4 assembly complete signal storing unit (30) and AAL 5 assembly complete signal storing unit (40), thereby to recognize an ALL3/4 reception complete and an ALL5 reception complete, if the interrupt signal is input.

Description

ATM communication type interrupt generator

1 is an example showing the configuration of an entire system to which the present invention is applied.

2 is a block diagram showing an interrupt generator of the ATM communication method according to the present invention.

3 shows the structure of a typical ATM cell.

(a) is a diagram showing the structure of the entire ATM cell.

(b) is a diagram illustrating an ATM cell header structure of a user network interface (UNI).

(c) shows the ATM cell header structure of the network node interface (NNI).

* Explanation of symbols for main parts of the drawings

1,1-1,1-2: I / O bus (SBUS) 2,2-1,2-2: Line workstation

4-1,4-2: ATM communication board 6: ATM switch

7: optical transmission line 10: AAL3 / 4 assembly completion signal generator

20: AAL5 assembly completion signal generator 30: AAL3 / 4 assembly completion signal storage unit

40: AAL5 assembly completion signal storage unit 50: interrupt signal generator

60: address decoder

The present invention relates to an ATM Adaptation Layer (AAL) that connects an ATM layer and a higher user service layer in an Asynchronous Transfer Mode (ATM) communication scheme. In particular, the present invention relates to an interrupt when an assembly of a received message is completed. The present invention relates to an ATM communication interrupt generator that generates a message to inform a higher layer of message reception.

Recently, as the means of communication is rapidly digitized and the development of optical communication enables the transmission of a wide band, a broadband ISDN (Broadband Intergrated Services Digital Network) has emerged to meet various user needs.

That is, B-ISDN is a video telephony service from narrowband services such as remote meter reading, data terminal, telephone, and facsimile, as described in broadband information communication (co-author Lee Byung-ki, Kang Min-ho, Jong-hee Lee; Kyohaksa; 1994; Seoul; p239 ~ 314). It is designed to handle and deliver broadband services such as video conferencing high-speed data transmission and video signal transmission in common, and is implemented based on an asynchronous transmission mode (ATM) communication method.

The ATM communication method is similar to the conventional packet communication method in that ATM cells are transmitted by cell unit by Asynchronous Time Division Multiplexing (ATDM). It handles even signal of bit rate and is standardized by international standardization organization for use in local area network as well as huge public network.

This ATM communication method is based on ATM cells as shown in (a) to (c) of FIG. 3, so that a user's long message is divided into ATM cells and transmitted. Reassembled into messages and delivered to the parent user.

That is, as shown in (a) of FIG. 3, an ATM cell is divided into a 5-byte (or octet) header section and a 48-byte user information section, and the 5-byte header is divided into (b) and (3) of FIG. As shown in c), the header structure is divided into a header structure at the user network interface (UNI) and a header structure at the network node interface (NNI) and a header structure at the user network interface (UNI). The first byte is composed of 4 bytes of Generic Flow Control (GFC) and 4 bytes of Virtual Path Identifier (VPI), and the second byte is 4 bytes of Virtual Path Identifier ( VPI) and 4-bit Virtual Channel Identifier (VCI), the third byte consists of 8-bit Virtual Channel Identifier (VCI), and the fourth byte is a 4-bit Virtual Channel Identification Number. (VCI), 3-bit payload type (PT) and 1-bit cell abandonment ranking (CLP: Cell Loss Priority, and the fifth byte is composed of 8-bit header error control (HEC).

Also, when looking at the header structure of the network node interface (NNI) as shown in FIG. 3 (c), the general flow control (GFC) in the first byte of the user network interface (UNI) described above identifies the virtual path. It can be seen that it is the same as the header structure of the user interface (UNI) except that it is used as a number (VPI).

This ATM communication method has a hierarchical structure as shown in Table 1 below, and has standardized standards for each layer.

As shown in Table 1, the ATM communication method is divided into vertical structures such as a physical layer, an ATM layer, an ATM adaptation layer (AAL), and a higher protocol layer, and the AAL layer is a cut and recombination sublayer (SAR). And the CS sublayer, and the physical layer is divided into a physical medium (PM) and a transmission convergence (TC) sublayer.

In addition, the services required by the user in the ATM communication method can be separated according to the characteristics of the source as shown in Table 2 below.

As shown in Table 2, the types of services in the B-ISDN are classified into Classes A to D according to the characteristics of the source. The Class A services are real-time, identity bit rate, and connectivity services. It is a variable bit rate, connectivity service, Class C service is a non-real time, variable bit rate, a non-connected service, Class D service is a non-real time, variable bit rate, a non-connected service. Representative examples of such services include identity rate video signals, variable rate video signals, connectivity data transmission, and connectionless data transmission.

On the other hand, AAL protocols corresponding to the above services are classified into AAL1 to AAL5 as shown in the following Table 3, but conventionally divided into AAL1 to AAL4, but AAL3 and AAL4 are similar to each other. AAL5 has been proposed to reduce the overhead.

As shown in Table 3, the AAL layer is divided horizontally as AAL1, AAL2, AAL3 / 4, AAL5 in order to efficiently process the service according to the type of service, and the AAL3 / 4 layer has a variable bit rate. It functions to deliver data of class C and class D service, and has message mode and stream mode, and transparently delivers service data unit (U-SDU) from service user, detects transmission error, identifies information and A convergence layer layer CS performing a buffer allocation function; The variable length data received from the convergence sub-layer CS is divided to form an ATM cell, delivered to the ATM layer, and further divided into a cutting and recombination sub-layer SAR that receives and reassembles the ATM cell from the ATM layer.

In addition, the Convergence (CS) sublayer is a Common Part Convergence Sublayer (CPCS) that performs functions common to the connectivity and connectionless services, and a Service Specific Convergence Layer (SSCS) for providing specific AAL user services. : Service Specific Convergence Layer).

Details of this AAL layer have been proposed in ITU-T Recommendations 1.362 and 1.363, and by Gigabit Networking: Craig Partridge; 1994; Addison Wesley; pp (61). 87) and Lee Byung-ki's two-person cooperative broadband communication (pp314 ~ 327).

On the other hand, in the interface between the AAL layer and the upper layer as described above at the time of receiving, since the function of notifying the upper layer of the reception of the message has been implemented in the past, the problem of processing a received message is slow. There was a problem that the computer is inefficient in order to execute the communication software.

Therefore, the present description has been drawn to solve the above-described conventional problems, and provides an ATM communication type interrupt generator that notifies the completion of message reception by generating a hardware interrupt when message reception is completed. have.

An interrupt generating apparatus of the present invention for achieving the above object comprises: an AAL3 / 4 assembling complete signal generator for generating an AAL3 / 4 assembling complete signal by receiving a segment type (STO) signal and a complete signal; An AAL5 assembly completion signal generator configured to input an end cell (m) signal and a complete signal to generate an AAL5 assembly completion signal; An AAL3 / 4 assembling complete signal storage unit for storing the output of the AAL3 / 4 assembling complete signal generator and transferring the output to the upper layer; An AAL5 assembly completion signal storage unit for storing the output of the AAL5 assembly completion signal generator and transferring the output to the upper layer; An interrupt signal generator for generating an interrupt signal INT when the AAL3 / 4 assembling complete signal or the AAL5 assembling complete signal is input; An address decoder for enabling the AAL3 / 4 assembly complete signal storage unit and the AAL5 assembly complete signal storage unit when a predetermined address is input; And a host computer that outputs a predetermined address when the interrupt signal is input, reads data of the AAL3 / 4 assembly completion signal storage unit and AAL5 assembly completion signal storage unit, and recognizes AAL3 / 4 reception completion or AAL5 reception completion. It is characterized by.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 shows an example of the configuration of the entire system to which the present invention is applied, and includes a plurality of line workstations 2-1 and 2-2 as host computers; ATM communication boards 4-1 and 4-2 connected to the line workstations 2-1 and 2-2 to provide communication according to an ATM method; An ATM switch 6 for forming a communication path between the ATM communication boards 4-1 and 4-2 is provided so as to exchange data at high speed in accordance with an ATM communication method between line workstations.

That is, when the application process of the sun workstation 2-1, which is the host computer of the upper layer, wants to transmit data to the other sun workstation 2-2, the data to be sent is determined according to the characteristics of the source (that is, the image to be sent). Data or computer data, etc.) Select the appropriate protocol (ie AAL1, AAL3 / 4, AAL5) to send a message through the I / O bus (SBUS: 1-1) to the AAL layer.

The AAL layer of the ATM communication board 4-1 inputs a message through an input / output bus (SBUS), divides the message into ATM cells as described above, and sends the message down to the ATM layer with various control information. The cell is transmitted to the ATM switch 6 using the optical transmission path 7 of the physical layer, and then through the physical layer and the ATM layer of the communication board 4-2 along the path formed by the ATM switch 6. Reach the opposite AAL layer. The ATM exchange and communication path setting are described in detail in the ATM Enhancement Technology Special Issue, Vol.19 No.8 (August 92).

On the other hand, the counterpart AAL layer reassembles the received ATM cell data, restores it into a single message, checks the CRC and sequence number, and checks whether an error has occurred during transmission. When the assembly of the received message is completed, the I / O bus (SBUS: 1-2) is interrupted to notify the sun workstation 2-2, which is the upper layer, of the completion of data reception. The line workstation 2-2 reads the received message and status information of the register set, checks whether an error occurs during transmission, and processes the received data. Data transmission between the layers is made through a first in first out (FIFO) register, and communication paths are established through a virtual path identifier (VPI) and a virtual channel identifier (VCI).

2 is a block diagram illustrating an upper layer interface device according to the present invention, in which an AAL3 / 4 assembly is received by receiving a STO signal and a complete signal from an AAL3 / 4 receiver that implements the AAL3 / 4 protocol. An AAL3 / 4 assembly completion signal generator 10 generating a completion signal; An AAL5 assembly completion signal generator 20 for receiving the last cell (m) signal and a complete signal from an AAL5 receiver implementing the AAL5 protocol and generating an AAL5 assembly completion signal; An AAL3 / 4 assembling complete signal storage unit 30 for storing the output of the AAL3 / 4 assembling complete signal generator 10 and transferring the output to the upper layer; An AAL5 assembly completion signal storage unit 40 for storing the output of the AAL5 assembly completion signal generation unit 20 and transferring the output to the upper layer; An interrupt signal generator (50) for generating an interrupt signal (INT) when the AAL3 / 4 assembly complete signal or the AAL5 assembly complete signal is input; An address decoder 60 for enabling the AAL3 / 4 assembly completion signal storage unit 30 and the AAL5 assembly completion signal storage unit 40 when a predetermined address is input; And outputs a predetermined address when the interrupt signal is input, reads data from the AAL3 / 4 assembly completion signal storage unit 30 and AAL5 assembly completion signal storage unit 40 to complete AAL3 / 4 reception completion or AAL5 reception completion. It has a line workstation 2 that recognizes it.

In FIG. 2, the AAL3 / 4 assembling complete signal generator 10 according to the present invention is implemented as an AND gate AND1 that logically multiplies a segment type STO signal with a complete complete signal. Output Here, the STO signal is a bit under the segment type (ST) signal, and the characteristics of the segments are separately displayed as shown in Table 4 below.

As shown in Table 4, if the segment type (ST) is '10', the 44-byte payload is data including the start of the message (that is, the CPCS header), and if it is '00', the middle part of the message is known. '01' indicates that the message is the end of the message (ie, including the CPCS trailer), and '11' indicates that the message is a single segment (CPCS header and CPCS trailer included in one segment).

Therefore, if the segment type signal STO is 1, it can be seen that the end segment is the end segment (EOM) or a single segment (SSM), and when the count of the last segment ends and a complete signal is generated, It can be seen that reception has ended. That is, when the STO is 1 and the complete signal is 1, the AAL3 / 4 assembly completion signal generator 10 according to the present invention outputs a result of logical multiplication.

On the other hand, in AAL5, the long message is divided into a plurality of ATM cells as described above. The inter-user bit (AUU: ATM_User To ATM_User) in the load form (PL) of the ATM cell is set to 1 in the last cell, and last, 0 if not a cell. Accordingly, as shown in FIG. 2, when the AUU bit of the ATM header is input as the last cell (m) signal and the count of the last cell is completed and the complete signal is 1, the assembly of AAL5 according to the present invention is completed. The signal generator 20 outputs 1 as a result of logically multiplying the two inputs.

In addition, the interrupt signal generator 50 combines the outputs of the AAL3 / 4 assembly completion signal generator 10 and the AAL5 assembly completion signal generator 20 so that one of the AAL3 / 4 assembly completion signal or the AAL5 assembly completion signal is generated. 1 generates an interrupt (INT) on the input / output bus (SBUS).

Here, the AAL3 / 4 assembly completion signal storage unit 30 and the AAL5 assembly completion signal storage unit 40 output the output of the AAL3 / 4 assembly completion signal generation unit 10 and the output of the AAL5 assembly completion signal generation unit 30. Difl-flops (32, 42) for storing each; Lines consisting of three-phase buffers 34 and 44 which output the outputs of the deflip-flops 32 and 42 to specific bits on the data bus in accordance with the buffer enable signal. Upon informing the workstation 2, the line workstation 2 outputs a predetermined address (e.g., 000007FFH) to the address decoder 40 to output the AAL3 / 4 assembly completion signal storage unit 30 and the AAL5 assembly completion signal. After the storage unit 40 is enabled, the stored data is read. Therefore, the upper layer, that is, the line workstation 2, reads the stored assembly completion signal when the interrupt (INT) is generated, determines whether the AAL3 / 4 message has been received or the AAL5 message has been received, and reads the corresponding data. Can be.

Here, for example, when the three-phase buffer 34 of the AAL3 / 4 assembly completion signal storage unit 30 is connected to B4 of the data bus, and the three-phase buffer 44 of the AAL5 assembly completion signal storage unit is connected to B7 of the data bus. In this case, the line workstation 2 reads both signals B4 and B7 with one address output, and it can be seen from which side the interrupt is generated.

As described above, the present invention implements the interrupt generators of the AAL3 / 4 receiver and the AAL5 receiver in hardware to generate an interrupt (INT) after message assembly is completed to inform the upper layer of the fact that the message has arrived. In addition, using AAL3 / 4 and AAL5 as the same interrupt increases the efficiency of interrupt use.

Claims (1)

In the ATM communication system layered into the physical layer, the ATM layer, the AAL layer and the upper layer, the data of the ATM cells received at the receiving end of the AAL layer is reassembled and message assembly is completed. An interface device between an AAL layer and a higher layer that notifies a message reception completion to process a received data, wherein the AAL3 receives an STO signal and a complete signal and generates an AAL3 / 4 assembling complete signal. / 4 assembling completion signal generator 10; An AAL5 assembling complete signal generator 20 which receives the last cell (m) signal and a complete signal to generate an AAL5 assembling complete signal; An AAL3 / 4 assembling complete signal storage unit 30 for storing the output of the AAL3 / 4 assembling complete signal generator 10 and transferring the output to the upper layer; An AAL5 assembly completion signal storage unit 40 for storing the output of the AAL5 assembly completion signal generation unit 20 and transferring the output to the upper layer; An interrupt signal generator (50) for generating an interrupt signal (INT) when the AAL3 / 4 assembly complete signal or the AAL5 assembly complete signal is input; An address decoder 60 which enables the human body to enable the AAL3 / 4 assembly complete signal storage unit 30 and the AAL5 assembly complete signal storage unit 40 when a predetermined address is input; And outputs a predetermined address when the interrupt signal is input, reads data from the AAL3 / 4 assembly completion signal storage unit 30 and AAL5 assembly completion signal storage unit 40 to complete AAL3 / 4 reception completion or AAL5 reception completion. An ATM communication interrupt processing apparatus, comprising a host computer 2 for recognition.