KR970012715A - Semiconductor memory device having data output circuit and data output adhesive pad - Google Patents

Semiconductor memory device having data output circuit and data output adhesive pad Download PDF

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Publication number
KR970012715A
KR970012715A KR1019950027742A KR19950027742A KR970012715A KR 970012715 A KR970012715 A KR 970012715A KR 1019950027742 A KR1019950027742 A KR 1019950027742A KR 19950027742 A KR19950027742 A KR 19950027742A KR 970012715 A KR970012715 A KR 970012715A
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KR
South Korea
Prior art keywords
data output
data
semiconductor memory
chip
memory device
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Application number
KR1019950027742A
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Korean (ko)
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KR0172433B1 (en
Inventor
이윤상
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김광호
삼성전자 주식회사
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Priority to KR1019950027742A priority Critical patent/KR0172433B1/en
Publication of KR970012715A publication Critical patent/KR970012715A/en
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Publication of KR0172433B1 publication Critical patent/KR0172433B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals

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  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

1. 청구 범위에 기재된 발명이 속하는 기술 분야1. TECHNICAL FIELD OF THE INVENTION

데이타 출력 회로와 데이타 출력 접착 패드를 갖는 반도체 메모리 장치에 관한 것이다.A semiconductor memory device having a data output circuit and a data output adhesive pad.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

본 발명은 반도체 메모리 장치의 데이타 출력 회로 예를 들면 데이타 출력 버퍼 혹은 데이타 출력 드라이버 및 데이타 출력 핀(패드)을 수직으로 배열하는 새로운 배치구조를 구현하여 다이(Die)크기를 최소한으로 억제하기 위한 데이타 출력 패드의 배치구조를 제공한다.The present invention implements a new layout structure for vertically arranging a data output circuit, for example, a data output buffer or a data output driver and a data output pin (pad) of a semiconductor memory device, thereby minimizing die size. Provide an arrangement of the output pads.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

본 발명은 칩내부의 데이타를 칩외부로 전송하는 통로인 다수개의 데이타 출력 핀과, 상기 데이타를 일련의 동작을 거쳐 일정한 데이타를 상기 칩외부로 전송하기 위한 데이타 출력 회로를 구비하는 반도체 메모리 장치에 있어서, 칩 중앙에 일렬로 배치되어 상기 데이타를 칩외부로 전송하며 상기 데이타 출력 핀과 접착하기 위한 다수개의 데이타 출력 접착 패드와, 상기 데이타 출력 접착 패드층의 일측에 배치되어 상기 데이타를 상기 데이타 출력 접착 패드로 소정의 전압레벨로 전송시키며 상기 데이타 출력 회로중 하나인 데이타 출력 드라이버와, 상기 데이타 출력 접착 패드층의 타측에 배치되어 상기 데이타를 상기 데이타 출력 드라이버로 전송하고 상기 데이타 출력 드라이버를 인에이블하는 상기 데이타 출력 회로중 하나인 데이타 출력 버퍼를 제공함에 있다.The present invention provides a semiconductor memory device comprising a plurality of data output pins, which are channels for transferring data inside a chip, to a chip, and a data output circuit for transferring certain data to the outside of the chip through a series of operations. And a plurality of data output adhesive pads arranged in a line at the center of the chip to transfer the data to the outside of the chip and to be bonded to the data output pins, and disposed at one side of the data output adhesive pad layer to output the data. A data output driver, which is one of the data output circuits, and is disposed on the other side of the data output adhesive pad layer to transfer the data to the data output driver and enable the data output driver. A data output burr which is one of the data output circuits It is to provide a.

4. 발명의 중요한 용도4. Important uses of the invention

반도체 메모리 장치에 적합하게 사용된다.It is suitably used for semiconductor memory devices.

Description

데이타 출력 회로와 데이타 출력 접착 패드를 갖는 반도체 메모리 장치Semiconductor memory device having data output circuit and data output adhesive pad

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 데이타 출력 회로 및 데이타 출력 접착 패드의 배치 구조도.2 is a layout diagram of a data output circuit and a data output adhesive pad according to the present invention;

Claims (2)

칩내부의 데이타를 칩외부로 전송하는 통로인 다수개의 데이타 출력 핀과, 상기 데이타를 일련의 동작을 거쳐 일정한 데이타를 상기 칩외부로 전송하기 위한 데이타 출력 회로를 구비하는 반도체 메모리 장치에 있어서, 칩 중앙에 일렬로 배치되어 상기 데이타를 칩외부로 전송하며 상기 데이타 출력 핀과 접착하기 위한 다수개의 데이타 출력 접착 패드와, 상기 데이타 출력 접착 패드층의 일측에 배치되어 상기 데이타를 상기 데이타 출력 접착 패드로 소정의 전압레벨로 전송시키며 상기 데이타 출력 회로중 하나인 데이타 출력 드라이비와, 상기 데이타 출력 접착 패드층의 타측에 배치되어 상기 데이타를 상기 데이타 출력 드라이버로 전송하고 상기 데이타 출력 드라이버를 인에이블하는 상기 데이타 출력 회로중 하나인 데이타 출력 버퍼를 구비함을 특징으로 하는 반도체 메모리 장치.A semiconductor memory device comprising a plurality of data output pins, which are passages for transferring data inside a chip to an outside of the chip, and a data output circuit for transferring certain data to the outside of the chip through a series of operations. A plurality of data output adhesive pads arranged in a line in the center to transfer the data to the outside of the chip and to be bonded to the data output pins, and disposed at one side of the data output adhesive pad layer to transfer the data to the data output adhesive pads A data output driving ratio which is transmitted at a predetermined voltage level and is one of the data output circuits, and is disposed on the other side of the data output adhesive pad layer to transfer the data to the data output driver and to enable the data output driver. With a data output buffer, one of the data output circuits A semiconductor memory device, characterized in that. 제1항에 있어서, 상기 데이타 출력 회로가 상기 데이타 출력 접착 패드와 상하로 인접하게 구성되어 상기 데이타의 전송거리를 짧게 함을 특징으로 하는 반도체 메모리 장치.2. The semiconductor memory device according to claim 1, wherein said data output circuit is arranged up and down adjacent to said data output adhesive pad to shorten the transfer distance of said data. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950027742A 1995-08-30 1995-08-30 Semiconductor memory device KR0172433B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950027742A KR0172433B1 (en) 1995-08-30 1995-08-30 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950027742A KR0172433B1 (en) 1995-08-30 1995-08-30 Semiconductor memory device

Publications (2)

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KR970012715A true KR970012715A (en) 1997-03-29
KR0172433B1 KR0172433B1 (en) 1999-03-30

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100412988B1 (en) * 2002-04-03 2003-12-31 주식회사 하이닉스반도체 Auto placement Designing method of semiconductor chip

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100412988B1 (en) * 2002-04-03 2003-12-31 주식회사 하이닉스반도체 Auto placement Designing method of semiconductor chip

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Publication number Publication date
KR0172433B1 (en) 1999-03-30

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