KR970011890B1 - Memory shared method of main processor and co-processor - Google Patents

Abstract

the first step of judging whether a sub-processor demands an external bus master; the second step of transferring bus demand data of the sub-processor to a main processor if the sub-processor demands the external bus master; the third step of transferring that the main processor acquires the bus after performing the second step; the forth step that the sub-processor transfers the start of a bus cycle to the main processor; the fifth step that the sub-processor accesses data of a memory by sharing the memory if the main processor recognizes the start of the bus cycle; and the sixth step of transferring a completion recognition data to the main processor when the data access by the sub-processor is completed.

Description

How to Share Memory Between Main Processor and Subprocessor

1 is a flowchart showing a memory sharing method according to the present invention.

FIG. 2 is a block diagram showing a configuration of a memory sharing apparatus to which the memory sharing method shown in FIG. 1 is applied.

3 is a waveform diagram of a signal related to FIG. 2;

* Explanation of symbols for main parts of the drawings

11: main processor 12: memory controller

13 bus controller 14 subprocessor

15: memory

The present invention relates to a method for sharing a memory between a memory controller by a main processor and a sub-processor controlling a LAN.

The main processor incorporating a memory controller includes a bus arbiter for a bus interface and a memory controller for accessing a memory. In constructing a computer system, it is very important to operate the system more efficiently by sharing system resources.

Accordingly, an object of the present invention is to provide a memory sharing method for sharing a memory between a main processor having a memory controller and a subprocessor controlling a LAN.

A memory sharing method of a main processor and a subprocessor according to the present invention for achieving the above object comprises: a first step of determining whether a subprocessor requires an external bus master; In a first step, when the subprocessor requests an external submaster, transferring a bus request data of the subprocessor to the main processor; A third step of, if the main processor acquires the bus after performing the second step, transferring it to the subprocessor; A fourth step of transmitting, by the subprocessor, the start of the bus cycle to the main processor after performing the third step; If the main processor recognizes the start of the bus cycle, the subprocessor shares the memory to access data in the memory; When the data access by the subprocessor is completed in the fifth step, the sixth step of transferring the data from the main processor to acknowledge the completion.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a flowchart illustrating a memory sharing method of a main processor and a subprocessor according to the present invention.

It is determined 31 whether the subprocessor requires an external bus master for accessing data in the memory. If the subprocessor requests the external bus master, it transmits the bus request data of the subprocessor to the main processor 32, otherwise it continuously monitors the request of the external bus master.

The main processor acquires a bus according to the bus request data of the subprocessor, and transfers the bus 33 to the subprocessor if the bus is obtained. The subprocessor communicates 34 the start of the bus cycle to the main processor in accordance with the bus acquisition of the main processor.

When the main processor recognizes the start of the bus cycle of the subprocessor, the subprocessor shares the memory and accesses 35 the data in the memory. When the data access by the subprocessor is completed 36, the data is passed 37 to the main processor to confirm completion.

2 is a block diagram of a memory sharing device including a bus controller controlled by the method of the present invention. The sharing of the memory 15 by the bus controller 13 via the LAN control bus 102 will be described.

The main processor may perform a bus request and a bus grant function for the internal DMA channel and any external DMA channel. External DMA Channel is BREQ The bus can be requested through the signal, and when the external bus is free, the BGNT signal is asserted to grant the bus to the external device. External device is BREQ You can dominate the bus while asserting the signal.

Before the subprocessor 14 can use the bus, it first issues a HOLD signal to request the acquisition of the bus from the main processor 11. The HOLD signal is transmitted to the BREQ via the bus controller 13. The signal is transmitted to the main processor 11. The main processor (11) is BREQ Upon receiving the signal, it recognizes that the external device is requesting a bus and generates a BGNT signal. The BGNT signal is passed to the subprocessor 14 and the bus controller (! 3) to indicate that the bus has been acquired. From this time, the subprocessor 14 may generate a bus control signal for accessing the memory 15, and recognizes the acquisition of the bus according to the BGNT signal to ADS. Generate a signal.

Bus controller 13 is ADS ADS along the signal A signal is generated and input to the main processor 11, and the ADS of the subprocessor 14 Since the signal is generated only for one clock cycle, the AS can be used for enough time to access the data. A signal is generated and input to the main processor 11.

The memory controller 12 embedded in the main processor 11 generates DRAS and DCAS, which are memory control signals 104, and the subprocessor 14 receives data from the memory 15 through the address / data bus 103. Can be accessed.

When the subprocessor 14 accesses data from the memory 15 to complete all tasks, the bus controller 13 reads READY. A signal is generated and input to the subprocessor 14. The subprocessor 14 deasserts the HOLD signal at the end of all operations and thus BREQ. Also deasserted. At this time, the main processor 11 deasserts the BGNT, and the main processor itself executes all control.

Table 1 shows the logic function of the bus controller for controlling the memory sharing device.

READY The signal is a data read signal input to the subprocessor and is reset. High, ADS Is high, and if STATE is S4, it is activated low to inform the subprocessor that the current data access operation is completed.

Table 1. Logic Function of Bus Controller]

AS Signal is ADS Occurs when a subprocessor becomes a busmaster, depending on the signal, to allow access to memory. At this time, AS Since the signal is not generated for as many cycles as required by the main processor, the AS Keep the signal low, making the data accessible from memory.

BUSEN The signal is input to the main processor to access data in memory when the subprocessor is the bus master. (Read Transaction), RD (Read Strobe), As Control to generate a control signal such as (Address Strobe).

LANWR The signal is LAN_RD, the read / write strobe signal when the bus is mastered from the subprocessor. According to the signal, enable the BE (Byte Enable) signal of the subprocessor connected to the DWE (Byte Write Enable Strobes) signal of the main processor. When the subprocessor becomes the bus master, the subprocessor runs on the BE signal to generate the memory write cycle of the main processor.

The state diagram flows from S1 to S4 according to the given conditions. In IDLE state, BGNT signal is high and AS Signal is low, REFRESH Signal is high, DRASO If the signal is high, it stops without going to the next state. If this condition is not satisfied, the state returns to S1.

DRASO in state S1 Signal is low, REFRESH If the signal is high, it continues to S2 state. DRASO Signal is high, REFRESH If the signal is low, memory refresh takes precedence over memory access, so state S1 is maintained until memory refresh is complete. If the BGNT signal goes low, the main processor informs it that it will not grant the bus and returns to the IDLE state.

ADS in state S3 If the signal goes low, it will request the bus again and return to state S1. Otherwise, the state S4 is continued.

FIG. 3 is a waveform diagram relating to the memory sharing apparatus shown in FIG. 3, and signal names for each are as follows. FIG. 3A is an MCLK signal, FIG. 3B is an address bus signal, FIG. 3C is a HOLD signal, and FIG. 3D is a BREQ. Signal, FIG. 3E is BGNT signal, FIG. 3F is ADS Signal, 3G or AS Signal, 3H or RD Signal, Figure 31 is RT Signal, FIG. 3J is a DRASO signal, FIG. 3K is a DCASO signal, and FIG. 3L is a READY Signal, and 3M is a data bus signal.

As described above, according to the present invention, the main processor and the subprocessor can operate while sharing the memory with each other.

Claims (1)

A method for sharing a memory between a main processor having a memory controller and a subprocessor controlling a LAN, the method comprising: a first step of determining whether the subprocessor requires an external bus master; A second step of transferring bus request data of the subprocessor to the main processor when the subprocessor requests an external bus master in the first step; A third step of, if the main processor acquires a bus after performing the second step, transferring the bus to the subprocessor; A fourth step of transmitting, by the subprocessor, the start of a bus cycle to the main processor after performing the third step; If the main processor recognizes the start of a bus cycle, the subprocessor shares a memory to access data in the memory; And a sixth step of transferring data from the main processor to completion of data access by the subprocessor in the fifth step.