KR970010646B1 - Sensing and decoding scheme for a bicmos read/write memory - Google Patents

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Description

BICMOS Decrypt / Write Memory

1 is an electrical diagram of a static constant velocity call memory (SRAM) using the present invention.

2 is an electrical schematic diagram of a conventional CMOS memory cell as can be used in the SRAM of FIG.

3 is an electrical schematic diagram showing a pair of bit lines together with a bit line pull-up circuit and a first stage sense amplifier.

4A and 4B are electrical diagrams illustrating a biasing state of a pull-up transistor during a read and write cycle according to the present invention.

FIG. 5 is a timing diagram illustrating operation of the column of FIG. 3 during a read and write cycle. FIG.

6 is an electrical diagram showing an interconnection state of a first stage and a second stage sense amplifier.

7 is an electrical schematic showing the interconnection state of a local data line pair and a first stage sense amplifier group.

8 is an electrical schematic of a second stage sense amplifier.

9 is an electrical schematic diagram of a circuit constructed in accordance with the present invention and for reducing the effect of power supply noise on the bit line of FIG.

10 is an electrical diagram showing a configuration of a pull-up control circuit according to the present invention.

11 is an electrical schematic diagram showing one of the blocks of a pull-up control circuit constructed in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

1: Static constant velocity call memory (SRAM) 2: Array

4: Address buffer 6: X decoder

8, 12: Y decoder 10: first stage sense amplifier

14 second stage sense amplifier 18 complementary data output line

20: input / output circuit 23: pull-up control circuit

24: CMOS static memory cell 25: reference voltage circuit

26, 30, 88a, 88b: p-channel transistor

28, 32, 45, 46a, 46b, 48a, 48b, 70, 72, 74, 92a, 92b: n-channel transistor

34,36: N-channel pass transistor 38: pull-up transistor

42a, 42b: emitter-coupled n-p-n transistor 63: delay stage

66, 68: Darlington transistor

76a, 76b, 78a, 78b, 86a, 86b: n-p-n transistor

82: inverter 90: inverting delay stage

TECHNICAL FIELD The present invention relates to the field of electronic integrated circuits, and in particular, to circuitry for use in a read / write memory device.

Integrated circuit memory devices are sometimes comprised of rows and columns of memory cells, which are selected based on the value of the memory address portion representing the row and column addresses, respectively. Within such devices, the term word line generally refers to a set of conductors that select an addressed row of memory cells when active, and the term bit line generally refers between a memory cell and a sense amplifier in an addressed row. Refers to a set of conductors that communicate data. The sense amplifier is a circuit that senses the data state of the data on the associated bit line and amplifies the sensed data state for communication to the output stage of the circuit.

Due to the drive capability of a static memory cell composed of latches, multiple columns in a static constant velocity call memory (SRAM) share a single sense amplifier. However, for sensing purposes, the shorter the bit line associated with a single sense amplifier, the smaller the differential voltage detectable by the sense amplifier. Therefore, for sensing purposes, it is desirable to provide a single sense amplifier for each column in a memory cell array.

However, the provision of multiple sense amplifiers needed to have one sense amplifier per column increases the load required to drive a particular sense amplifier. For example, within a 256kbit SRAM of 256 rows x 1024 columns, 1024 sense amplifiers must be provided for a one-to-one correspondence between sense amplifiers and columns. Therefore, the sense amplifier associated with the selected column must be able to drive data lines accessible to 1023 other sense amplifiers. These long data line capacitive loads, including parasitic loads provided by isolation transistors that separate the unselected sense amplifiers from the data lines, require the provision of many drive transistors in each sense amplifier or attenuate read access time performance. . Within the architecture in which a single sense amplifier is provided for each column, the space required for the sense amplifier, which is a given dimension (i.e., sense amplifier pitch), is hardly extended to the integrated circuit size needed to use the SRAM device, but the array of memory cells. It can be less than the space (i.e., column pitch) needed to provide the N, which of course limits the size of the drive transistors that can be provided in the sense amplifier.

It is therefore an object of the present invention to provide a sensing and decoding technique for static RAM devices that reduces the data line load for sense amplifiers.

Another object of the present invention is to provide a sensing and decoding technique for SRAM having a single sense amplifier for each column of memory cells.

Another object of the present invention is to provide a sensing and decoding technique realized with BICMOS technology.

Moreover, sense amplifiers of such memory circuits are generally required to sense small differential voltages between a pair of bit lines to which a selected memory cell is connected. For speed, each bit line in this pair of bit lines is precharged to a predetermined voltage and equalized by connecting the bit lines in the pair of bit lines to each other for a short period after the precharge operation. In conventional static constant speed call memory (SRAM), pull-up devices are connected between each bit line and the power supply, which pull-up devices have a low bit state in the bit line pair. It is used to help pull a bit line in the bit line pair high while being pulled to, and the selection of which bit line goes high depends on the sensed data state of the addressed memory cell. Within BICMOS SRAMs, bipolar transistors are well used as fall-up devices because they have fast switching characteristics (at least one diode drops to a voltage that falls below the positive power supply level). This is because it acts as a diode clamp for the bit line (which holds the higher bit line in).

However, the diode characteristics of a bipolar pull-up device present a problem when noise is present on the positive (Vcc) power supply to which the pull-up transistors are connected. Due to the bipolar pull-up transistor acting as a diode, the positive noise on Vcc pulls the two bit lines to high voltage and the negative noise on Vcc does not affect the voltage on the bit line. . After a bump of positive noise on Vcc pulls two bit lines to a high level, a readout cycle causes one bit line in the bit line pair to pull to a low level, while the other bit lines are bumped voltages. Will be maintained. The positive bump is so large that the precharge and equalization operation, i.e., the pull-up of the bit line by the pull-up transistor is insufficient to fully equalize the bit lines at the end of the cycle. Failure may occur within the cycle. In the case of fully corrected RAM, this failure occurs when the bit line differential voltage due to noise is so large that the memory cell has insufficient time to set the bit line voltage of the correct polarity.

It is therefore an object of the present invention to provide a bit line pull-up circuit having a bipolar pull-up device but allowing perturbation of the biasing power supply.

Write operations to a particular memory cell are generally accomplished by pulling one bit line of a pair of bit lines to a low level (Vee) and pulling another bit line to a high voltage level (Vcc-Vbe). After the write cycle, the bit lines must be pulled up by the bipolar pull-up transistors to the same potential with respect to each other in preparation for the next read cycle. However, the large differential voltage of the bit line after writing requires very many pull-up devices or long pull-up periods, which are undesirable.

It is therefore another object of the present invention to provide a bit line pull-up circuit that reduces the bit line differential voltage during a write cycle to accelerate the recovery of the bit line to the next equivalent voltage.

Another object of the present invention is to provide such a pull-up circuit used in BICMOS technology.

Another object of the present invention is to provide such a pull-up circuit in the form of one sense amplifier per column of memory cells.

Another object of the present invention is to provide such a pull-up circuit which reduces the bit line differential voltage and improves the perturbation tolerance of the Vcc power supply.

The present invention can be used in a BICMOS SRAM read / write memory having a pair of complementary bit lines associated with each column of memory cells, and a first stage sense amplifier associated with each column. The first stage sense amplifiers are arranged in groups, with each first stage sense amplifier in the group driving a common complementary data line pair. A second stage sense amplifier is provided for each group, and all second stage sense amplifiers drive a pair of global data lines. The column address is decoded to select one sense amplifier of the first stage sense amplifiers and one sense amplifier of the first stage sense amplifiers, wherein the unselected first stage sense amplifiers are disabled and set to the local data line. To provide impedance. The multiple maximum significant bits of the column address are used to enable a second stage sense amplifier associated with the group containing the selected first stage sense amplifier, disabling the other second stage sense amplifiers, and writing to the global data line. Provide impedance.

The invention can be used in a BIlCMOS SRAM read / write memory associated with each column of memory cells and having a pair of complementary bit lines, each having a bipolar transistor for a pull-up device. Since a pull-up circuit is provided that acts as a low pass filter for noise perturbation on the power supply line, positive noise on the power supply will not pull the bit line voltage above the equivalent value. Since another pull-up circuit is provided that controls the base drive of the pull-up transistor during the write cycle, the base drive of the pull-up transistor associated with the higher bit line of the bit line pair is reduced, so that it is more within the next read cycle. It will provide a short crossover time.

Referring to FIG. 1, a schematic diagram of a static constant velocity call memory (SRAM) 1 is shown. This embodiment of the SRAM 1 is a 256K bit memory having a single input / output terminal I / O. The SRAM 1 is configured as 256K x 1 memory. The memory elements of the SRAM 1 are included in the array 2 composed of 256 rows x 1024 columns in this embodiment. The SRAM 1 receives address information on the address input An. To individually address each bit in 256K bit memory, the number of address input An is 18. Of course, if more than one bit is accessed at a time (e.g., configured as 32Kx8 memory having eight inputs and eight centers of 256K bit SRAM (l)), fewer address inputs An are required.

The address input An is received by the address buffer 4 which latches and holds the address value externally provided to the address input An as known in the art. Eight of the eighteen address bits received by the address buffer 4 (these eight bits correspond to a row address) are the X decoder to select one of the 256 rows in the array 2. Is communicated to (6). The remaining ten bits received by the address buffer 4 corresponding to the column address are one of 1024 columns in the array 2 to be sensed by one of the 1024 first stage sense amplifiers 10. It is communicated to the first stage Y decoder 8 to select a column. Each of 1024 columns, or 1024 first stage sense amplifiers, is associated with a complementary bit line pair as described below, and a selected sense amplifier of the 1024 first stage sense amplifiers senses the differential voltage of the complementary bit line. A bank of bit line pull-up transistors 21 is provided in the SRAM 1 as described later.

In addition, five column address bits of the ten column address bits are communicated to the second stage Y decoder 12 to select one second stage sense amplifier 14. Although FIG. 1 shows two separate Y decoders 8 and 12, a second stage Y decoder 12 may be used in the first stage Y decoder 8. This use requires that multiple decoding stages are required in the first stage Y decoder 8 and a break between the internal decoder stages is necessary to select one of the second stage sense amplifiers 14. When performed at a point, the second stage sense amplifier (not only selects a suitable second stage sense amplifier 14, but also selects one of the first stage sense amplifiers 10 upon decoding the column address signal). 14) will be used. The 1024 first stage sense amplifiers 10 are grouped into 32 groups, each group having complementary local data lines 16 pairs as outputs. One of the second stage sense amplifiers 14 is associated with each group of 32 first stage sense amplifiers and receives at its input an associated pair of local data lines 16. The complementary data output line 18 pair is driven by a second stage sense amplifier 14. In operation, the first stage sense amplifier 10 corresponding to the column address is enabled by a signal from the first stage Y decoder 8, the Y decoder 8 being associated bit lines from the array 2. By sensing the data state of the pair, the remaining first stage sense amplifier 10 is disabled. One of the second stage sense amplifiers 14 corresponding to the first stage sense amplifier 10 group having the selected column is enabled, and the remaining second stage sense amplifiers 14 are disabled. A selected one of the second stage sense amplifiers 14, on the data output line 18, amplifies the differential voltage on the local data line 16 at its input to communicate to the input / output circuit 20. Provide a differential voltage that is a voltage. The input / output circuit 20 communicates the state of the data output line 18 to the input / output terminal I / O.

Also, the SRAM 1 input / output circuit 20 of FIG. 1 receives input data from the input / output terminal I / O, and the determination of whether a read cycle is required or a write cycle is required is made. It depends on the state of the terminal R / W_ connected to the circuit 20. During the write cycle, the input / output circuit 20 provides a logic state externally provided to the input / output terminal I / O on the data input bus 22, so that the input / output circuits 20 Provide true and complementary conditions to the first stage sense amplifier 10. The data input bus 22 is also connected to the pull-up control circuit 23 for performing the write recovery operation described later.

The SRAM 1 also has a reference voltage circuit 25 that receives the power supply voltages Vcc and Vee (ground potential). The power supply voltages Vcc and Vee are routed to transistors across the SRAM 1 for biasing purposes, which routing is not shown in FIG. 1 for clarity. A particular embodiment of the SRAM 1 described herein is a BICMOS SRAM using two bipolar transistors as well as p-channel and n-channel MOS transistors. Certain circuits in this embodiment of the SRAM 1 are realized with emitter-coupled logic. When emitter-coupled logic is used, the reference voltage circuit 25 provides a band-gap reference voltage.

Referring to FIG. 2, a conventional CMOS static memory cell 24 as shown in a BICMOS SRAM is shown. The memory cell 24 is constituted by a known cross-coupled inverter, and since a p-channel and n-channel transistor can be used, a CMOS inverter is used in the memory cell 24. The first CMOS inverter in the memory cell 24 is formed of a p-channel transistor 26 and an n-channel transistor 28 in which source-drain paths are connected in series between Vcc and ground, and gates are coupled to each other. do. The second CMOS inverter in the memory cell 24 is similarly configured, with the source-drain paths of the p-channel transistor 30 and the n-channel transistor 32 connected in series between Vcc and ground, the gates being common. . Cross-coupling of gates of transistors 26 and 28 (node S1 in FIG. 2) connected to the drains of transistors 30 and 32, and of transistors 30 and 32 connected to the drains of transistors 26 and 28, respectively. This is achieved by the gate (node S2 in FIG. 2). The source-drain path of the N-channel pass transistor 34 is connected between the node S1 and the first bit line BL, and the gate is connected to the word line WL. Similarly, the source-drain path of the N-channel pass transistor 36 is connected between the node S2 and the second bit line BL_, and the gate is connected to the word line WL.

In operation, the voltages of nodes S1 and S2 necessarily become logical complements of each other due to the cross-coupling characteristics of the CMOS inverters in memory cell 24. When the word line WL is activated by the X decoder 6 shown in Fig. 1, according to the row device received at the address input An, the pass transistors 34 and 36 are turned on, so that the nodes S1 and S2 are bitlined. To BL and BL_. Thus, the states of the bit lines BL and BL_ become logical complements of each other when the memory cells 24 are connected by activation of the word line WL.

As described above for this embodiment, there are 256 word lines WL and 1024 bit lines BL and BL_pairs in the array 2 of FIG. For each value of the row address decoded by the X decoder 6, one word line SL is activated to connect 1024 memory cells 24 to 1024 bit lines BL and BL_pairs. Since the other 256 word lines WL are at the low logic level, only one memory cell 24 associated with the selected word line WL in each column is connected to the bit lines BL and BL_pair at a time.

Referring to FIG. 3, the columns of the array 2 are shown. For clarity, only two memory cells 24 are shown with only two word lines WLn and WLn + ₁ , as described above, each column has 256 memory cells 24 associated with 256 independent word lines WL. Has Within the column shown in FIG. 3, cell 24 is shown connected to complementary bitlines BL and BL_. Bit lines BL and BL_ are connected to the first stage sense amplifier 10 and are connected to Vcc via npn pull-up transistors 38a and 38b, respectively. The pull-up transistor 38 corresponds to the bit line pull-up transistor 21 shown in FIG. The base of the pull-up transistors 38a and 38b is driven by a pull-up control circuit 23 that receives input data clocked from the input / output circuit 20 on the data input bus 22.

The first stage sense amplifier 10 consists of two emitter-coupled n-p-n transistors 42a and 42b whose base is connected to the bit lines BL and BL_. The emitters of transistors 42a and 42b are connected to the drain of n-channel transistor 45 whose source is coupled to ground and whose gate is connected to line YSEL. Transistor 45 is turned off when a column is not selected (ie, when line YSEL is low) and turned on to act as a current source when a column is selected (ie, when line YSEL is high). Line YSEL is also connected to p-channel transistor 47 which acts to equalize bit lines BL and BL_ when transistor 47 is on due to the low state of line YSEL. The line YSEL, in the case of a particular column, is low during a cycle in which no column is selected, thereby equalizing the bit lines BL and BL_. The collectors of transistors 42a and 42b are connected to local data lines 16_ and 16, respectively. As described above for this embodiment, the 32 first stage sense amplifiers 10 share local data lines 16 and 16_. Local data lines 16 and 16_ are pulled up to Vcc by resistor 44.

A particular column write circuit consists of n-channel transistors 48a and 48b with source-drain paths connected in the path between bit lines BL and BL_ and ground. The gates of n-channel transistors 48a and 48b are controlled by data input lines 22 and 22_, one of which is at a high logic level at the time the write operation occurs. The choice between the data input lines 22 and 22_ depends on the input data received at the input / output terminal I / O. During the read cycle, data input lines 22 and 22_ remain at a low logic level. The N-channel transistors 46a and 46b are connected in series between the transistors 48a and 48b on the one hand and connected to the bit lines BL and BL_ on the other hand. Since the gates of transistors 46a and 46b are controlled by line YSEL, the state of data input lines 22 and 22_ only affects a selected one of the 1024 columns and is separated from the other columns.

4A shows an equivalent circuit for the selected column of FIG. 3 in a decryption operation. 5 is a timing diagram showing the operation of the read cycle in the first cycle. During the read cycle, the data input lines 22 and 22_ of FIG. 3 go to a low logic level. In response, the pull-up control circuit 23 will provide Vcc to the bases (nodes A and B in FIGS. 4A and 5) of the pull-up transistors 38a and 38b, respectively. At the emitter of 38b)

Is the same as Vcc-Vbe, where Vbe is the forward-biased diode drop across the base-emitter junction. The memory cell 24 selected by the word line WL provides a differential voltage on the bit lines BL and BL_. This description is for the case where the bit line BL is higher than the bit line BL_. Therefore, since the bit line BL is higher than the bit line BL_, the associated first stage sense amplifier transistor 42a is turned on more than the transistor 42b associated with the bit line BL_. Since the transistor 45 is on and acts as a current source to keep the sum of the currents through the transistors 42a and 42b constant, the high drive at the base of the transistor 42a causes most of the current through the transistor 45. Flows through transistor 42a in relation to transistor 42b. Due to the pull-up transistors 38a and 38b, as shown in FIG. 5, the bit line BL maintains almost Vcc-Vbe, and the bit line BL_ has a slight drop in voltage.

Since most of the current through transistor 45 in relation to transistor 42b is through transistor 42a, local data line 16_ is pulled low, and local data line 16 is transistor 42b. The minimum drive through maintains high. Each transistor 45 of the other first stage sense amplifier 10 sharing the local data lines 16 and 16_ is turned off, so only the transistors that pull down one of the data lines 16 and 16_ Transistors 42a or 42b driven by bit lines BL and BL_ that are high states associated with the selected column.

FIG. 4B shows an equivalent circuit during the write operation for the column constructed in accordance with the present invention and shown in FIG. One of the data input lines 22 or 22_ is pulled to a high level by the input / output circuit 20 in accordance with the input data received at the input / output terminal I / O, the examples described herein. In, data input line 22 is pulled to a high logic level during a write operation. This occurs at time t _{w shown} in FIG. Thus, transistor 48b in the column of FIG. 3 is turned on in data input line 22, since transistor 48b is asserted to a high level in the case of the selected column, transistor 48b writes as shown in FIG. 4b. Select bit line BL_ to be pulled to low level for execution.

According to the invention, the pull-up control circuit 23 provides different bias levels to the base of the pull-up transistors 38a and 38b depending on the data state to be written, which is at time t _w at the start of the write operation. Is initiated. At node B, i.e. at the base of transistor 38b, the pull-up control circuitry provides a Vee, because transistor 38b has a high level of data input line 22 (not line 22_). This is because it is related to the bit line BL_ to be pulled to a low level because According to the invention, starting at time t _w , pull-up control circuit 23 applies a voltage to node A (base of transistor 38a) that is reduced from the bias applied during the read cycle.

Within this embodiment, the applied voltage is one diode drop voltage Vbe of less than Vcc due to transistor 50a biasing the base of transistor 38a. Thus, on the high bit line (in this case, the bit line opposite the bit line pulled to the low level, which is the bit line BL), the pull-up transistor 38a is biased to be in a conductive state, so the pull-up transistor 38a The voltage at the emitter is a reduced voltage relative to the readout cycle. In this case, the voltage of the high bit line BL is Vcc-2Vbe during the write operation, and the voltage of the low bit line BL_ is pulled down to Vee.

Writing is accomplished after transistors 46b and 48b pull bit line BL_ to Vee and set node S2 (see also FIG. 2) in memory cell 24 to a low level, thus writing into memory cell 24. The cross-coupled inverter latches the required data state. The low level on bit line BL_ turns off transistor 42b in first stage sense amplifier 10. In transistor 42a, even though all currents allowed through transistor 45 (the base voltage of this transistor is a voltage Vcc-2Vbe sufficient to keep transistor 42a on) pass through, The current allowed into the base is limited so that the bit line BL maintains the voltage Vcc-2Vbe. The influence of the low level of the bit line BL_ through the transistors 46b and 48b ignores the first stage sense amplifier 10, writing the required data into the memory cell 24. When the parasitic capacitances of the node S2 of the memory cell 24 and the bit line BL_ are discharged, the voltage of the bit line BL_ drops to the voltage Vee as shown in FIG.

The advantage of the reduced bias of transistor 38a on high bit line BL during a write operation is evident after the write operation and before the read operation (ie, the write recovery time).

Referring to FIG. 5, the write cycle begins to end at time t _r , where one of the data input lines 22 or 22_ (in this case, line 22) goes from the high logic level to the low logic level. do. Within this example, this turns off the transistor 48a, separating the bit line BL_ from Vee and responding to the pull-up transistor 38b. In addition, in response to the data input line 22 returning to the low level, the pull-up control circuit 23 returns the bias on the bases (nodes A and B) of the transistors 38a and 38b to Vcc. In the case of a bit line that is low in the previous write cycle, for example bit line BL_, this biasing of pull-up transistor 38b is, as in the above-described readout cycle, bit lines BL_ and Vcc. Pull back up towards Vbe. In the case of a bit line that is high in the previous write cycle, for example bit line BL, the biasing of pull-up transistor 38a causes Vcc-2Vbe to replace bit line BL, as in the above-described readout cycle. Vail the Vcc-Vbe again.

In the case where the data state of the selected memory cell 24 is the same state as the state written by the write cycle, the two bit lines BL and BL_ become differential voltage again as shown in the first read cycle of FIG. . In this example, the speed does not improve at all because the voltages of the bit lines BL and BL_ do not cross before they are set to the read state. However, when the data read out by the second read cycle is opposite to the data written by the write cycle, the voltages of the bit lines BL and BL_ are on the base of the pull-up transistor 38 on the high side during the write cycle. The reduced bias results in an intersection earlier than after t _r . This case is shown in the second read cycle in FIG. 5 and assumes that memory cells 24 in a row different from the rows written in the write cycle are decrypted in the second read cycle (to decrypt the different data). do.

The high side bit line, in this case bit line BL, is pulled-up transistor 38a from low voltage (Vcc-2Vbe) to high voltage (Vcc-Vbe-dV; dV is the delta voltage due to the low side bit line in the read cycle. ), The intersection between the voltage of the bit line BL and the voltage of the bit line BL_ occurs at time t _{s shown} in FIG. At the intersection point t _s , the first sense amplifier 10 will flip to the appropriate data state as described above, because the bit line on the high side (in this case, bit line BL_) on the low side achieves decoding. This is because the related transistor 42 is driven more difficult than the bit line BL. If the high side bit line (eg, bit line BL) from the previous write cycle falls from voltage Vcc-Vbe, which is the same voltage as during the read cycle, the intersection with the rising bit line BL_ does not occur until after t _s. Will not. The waveform BL 'shown in FIG. 5 shows the characteristics of the bit line BL when the write bias on the transistor 38a is the same between the read cycle and the write cycle, and later the intersection is shown as time t _s ' in FIG. It is. Due to the bias change on the high side pull-up transistor, the access time is improved by the time difference between time t _s ' and time t _s .

Referring to FIG. 6, the interconnection of the first stage sense amplifier 10 group with the local data line 16 and the associated second stage sense amplifier 14 is described. As described above, the 1024 first stage sense amplifiers 10 ₀ to 10 ₁₀₂₃ are grouped into 32 groups, and the first stage sense amplifiers 10 ₀ to 10 ₃₁ are the first group of first stage sense amplifiers ( 10 ₃₂ to 10 ₆₃ ) is the second group,. And so on. The output of each first stage sense amplifier 10 in the group is wire-AND to a pair of common complementary logic data lines 16 and 16_. Each pair of local data lines 16 from the first stage sense amplifier 10 group is provided at the input of a second stage sense amplifier 14 associated with this group. For example, second stage sense amplifier 14 ₀ receives local data lines 16 and 16_ from first stage sense amplifiers 10 ₀ to 10 ₃₁ .

One of the 1024 first stage sense amplifiers is selected according to ten bits of the column address to sense memory cells in the associated column in the selected row. This selection is based on the value of the 10-bit column address received at the address input An of FIG. 1, in order to communicate a unique select line YSEL (not shown) to the respective first stage sense amplifiers 10. Achieved by the decoder 8. The unselected first stage amplifier 10 is not enabled and provides high impedance to two complementary local data lines 16. The result of the sensing operation performed by the selected sense amplifier of the first stage sense amplifiers 10 is on the pair of local data lines 16 by one of the pair of line pairs pulled to a low level as described in detail below. Is provided.

The second stage sense amplifier 14 corresponding to the first stage sense amplifier 10 group including the first stage sense amplifier 10 selected by the column address is enabled, providing a differential provided on the local data line 16. Amplify the voltage and provide this amplified differential voltage to the complementary data output line 18 and 18_ pair. The selection, within this example, receives the five most significant bits of the column address, and selects one of the selection lines SSL0 to SSL 31 to enable the second stage sense amplifier 14 to enable the second stage sense amplifier ( 14 is performed by the second stage Y decoder l2 asserting to 14). The outputs of the second stage sense amplifier 14 are wire-ORed to each other at the data output lines 18 and l8_. The unselected sense amplifiers of the second stage sense amplifier 14 are disabled and provide high impedance to the two data output lines 18, so that the selected sense amplifiers of the second stage sense amplifier 14 are data output lines. To set the state of (18 and 18_). As shown in FIG. 1, data output lines 18 and 18_ are received by input / output circuit 20 to communicate to input / output terminal I / O.

Referring to FIG. 7, the thermal decoding and sensing technique of this embodiment of the SRAM 1 is described. According to this embodiment of the present invention, as described above with reference to FIG. 1, one first stage sense amplifier 10 is associated with each of 1024 columns in the array 2. The first stage sense amplifier 10 is grouped into 32 groups of 32 first stage sense amplifiers 10. 7 shows the interconnection state of one group of 32 first stage amplifiers 10 and the driving state of the complementary local data line 16.

The first stage sense amplifiers 10 ₀ to 10 ₃₁ are shown schematically in FIG. As shown in FIG. 3, each of the first stage sense amplifiers includes transistors 42a and 42b having a base connected to bit lines BL and BL_ and a collector connected to local data lines 16_ and 16. FIG. Have Emitters of transistors 38a and 38b are connected to each other to couple to Vee through transistor 45. Each first stage sense amplifier 10 receives a unique select signal on the line YSEL from the first stage Y decoder 8 at the gate of the transistor 45. For example, first stage sense amplifier 10 ₀ receives line YSEL ₀ and first stage sense amplifier 10 ₁ receives line YSEL ₁ . As mentioned above, each of the 1024 first stage sense amplifiers receives a unique select signal on its associated line YSEL _n ( _where n is 0 to 1023), because the SRAM 1 described is 256K X. Therefore, only one sense amplifier of the first stage sense amplifiers 10 is enabled for a predetermined read operation by the high logic level on the associated select line YSEL, and the remaining unselected. The first stage sense amplifier 10 receives a low logic level on select line YSEL.

In the case of the group shown in FIG. 7, if none of the lines YSEL ₀ to YSEL ₃₁ are asserted by the first stage Y decoder 8, all transistors for the first stage sense amplifiers 10 ₀ to 10 ₃₁ ( 45) are turned off. In this case, resistor 44 pulls two local data lines 16 and 16_ to Vcc, because either of the first stage sense amplifiers 10 ₀ to 10 ₃₁ pulls the line to a low level. It is not enabled.

If one of the first stage sense amplifiers 10 ₀ to 10 ₃₁ in the group shown in FIG. 7 is selected, the unselected first stage sense amplifiers 10 in this group are associated with the select line. Receiving the low logic level on YSEL keeps each transistor 45 in the unselected first stage sense amplifier 10 off. However, in the case of the selected sense amplifier of the first stage sense amplifiers 10, a high logic level is received on the select line YSEL and its transistor 45 is turned on, on the associated bit line BL and BL_pair. The differential voltage is detected. For example, doemeuro first stage sense amplifier (10 ₁₎ is chosen, because the line YSEL ₁ assuming a high logic level, the transistor is (45) is turned on in the first stage sense amplifier (10 _1). Thus, as described above, _one of the transistors 42a and 42b associated with the bit lines BL ₁ and BL_ ₁ in the high state is a transistor 42a or 42b associated with the bit lines BL ₁ and BL_ ₁ in the low state. More turned on, the polarity of the differential voltage changes depending on the data state stored in memory cell 24 in the selected row. For example, if the selected memory cell 24 stores data that causes the bit line BL ₁ to go high with respect to the bit line BL_ ₁ , then the transistor 42a in the first stage sense amplifier 10 ₁ is a transistor ( 42b), it is turned on more strongly to regulate the conduction amount of the current passed by the transistor 45 acting as a current source. Therefore, transistor 42a acts to pull down local data line 16_, and pulling down local data line 16_ is not selected first stage sense amplifiers 10 ₀ and 10 ₂ to 10 ₃₁ . Is not strongly influenced by the transistors because the transistors 45 are off. Since the conduction through the transistor 42b in the first stage sense amplifier 10 ₁ is minimal due to the influence of the transistor 45, the local data line 16 remains in a high state, so that the first stage sense amplifier ( The result of the sensing operation by 10 ₁ ) is communicated to the second stage sense amplifier 14 ₀ .

Referring to FIG. 8, the configuration and operation of the second stage sense amplifier 14 will be described. On the input side of the second stage sense amplifier 14, the local data line 16 has a collector connected to Vcc and an emitter connected to the base of the npn transistor 76a and the drain of the n-channel transistor 70. It is connected to the base of the npn transistor 78a. The collector of transistor 76a is connected to Vcc via pull-up resistor 80 and the emitter is connected to the drain of n-channel transistor 72.

Similarly, the local data line 16_ has an npn transistor 78b having a collector connected to Vcc and an emitter connected to the base of the npn transistor 76b and the drain of the n-channel transistor 74. Is connected to the base. The collector of transistor 76b is connected to Vcc through another pull-up resistor 80 and the emitter is connected to the drain of n-channel transistor 72. The sources of transistors 70, 72 and 74 are connected to Vee. The line SSL from the second stage Y decoder 12 is connected to the gates of the n-channel transistors 70, 72 and 74.

In operation, if the second stage sense amplifier 14 is not selected by the second stage Y decoder 12, the line SSL is at a low logic level. Since transistors 70, 72 and 74 are all turned off, none of n-p-n transistors 78 and 76 pass current, regardless of the state of local data lines 16 and 16_. Thus, nodes SA and SB at the collectors of transistors 76a and 76b are pulled to Vcc through resistor 80 in an unselected state.

If the second stage sense amplifier 14 is selected. Line SSL is in a high logic state, causing transistors 70, 72, and 74 to turn on. Within the selected condition, the input side of the second stage sense amplifier 14 is enabled to detect the differential voltage between the local data lines 16 and 16_. Transistors 78a and 78b communicate the voltage of local data lines 16 and 16_ to the bases of transistors 76a and 76b, which are reduced by the base-emitter diode voltage drop Vbe. Therefore, the input side of the second stage sense amplifier 14 is operated in the same manner as the first stage sense amplifier 10, with the transistor 72 serving as a current source for the emitter-coupled transistors 76a and 76b. In the above-described example, in the case where the local data line 16 has a higher voltage than the local data line 16_, most of the current passed by the transistor 72 causes the transistor 76a, not the transistor 76b. Will pass. Thus, within this example, node SA is in a lower voltage state than node SB.

Considering the output shaft of the second stage sense amplifier 14, the p-channel transistor 88a has a node SA connected to its drain, and the source of this transistor is connected to the base of the n-p-n transistor 86a. Similarly, node SB is connected to the drain of p-channel transistor 88b whose source is connected to the base of n-p-n transistor 86b. The collectors of transistors 88a and 88b are connected to Vcc, and the emitter is connected to data output line 18_.

And 18). The bases of the transistors 86a and 86b are connected to the drains of the n-channel transistors 92a and 92b whose sources are connected to Vee, respectively.

The line SSL inverted by the inverter 82 is connected to the gates of the transistors 88a and 88b. In addition, the line SSL is connected to the gate of the transistor 92. Each second stage sense amplifier 14 has a pair of n-channel transistors 94a and 94b, whose source-drain paths are connected between data output lines 18_ and 18 and Vee. The output of the inverter 82 drives the gates of the transistors 94a and 94b via the inverting delay stage 90. Inverting delay stage 90 consists of a CMOS inverter having a relatively small p-channel pull-up transistor and a relatively large n-channel transistor pull-down transistor. This causes the inverting delay stage 90 to have a delay for only one transition, and the output of the inverting delay stage 90 speeds up the high-low transition for the reasons described below, while the low-high transition is relatively slow. Let's do it.

In operation, if the second stage sense amplifier 14 is not selected, the output of the inverter 82 is at a high logic level. Thus, transistor 88 is turned off and transistor 92 is turned on, pulling the base of transistor 86 to Vee, thereby turning these transistors off. Thus, the second stage sense amplifier 14 provides high impedance to the data output lines 18 and 18_, with the remaining sense amplifiers of the 32 second stage sense amplifiers 14 being the second shown in FIG. However, it is connected to the data output lines 18 and 18_ in a manner similar to the sense amplifier 14. In addition, since transistors 94a and 94b are also turned off (in a stopped state), the second stage sense amplifier 14, which is not selected, provides high impedance to data output lines 18 and 18_. Therefore, the connection of the data output lines 18 and 18_ to the 32 second stage sense amplifiers 14 is a wired-OR characteristic, and any of the second stage sense amplifiers is a data output line 18 or 18_. Can be pulled up, and the unselected second stage sense amplifier 14 will provide a high impedance to this data output line.

When the second stage sense amplifier 14 is selected, the output of the inverter 82 is at a low logic level, turning on the transistors 88a and 88b. Transistors 92a and 92b are turned off so that the full differential voltages of nodes SA and SB are provided to the gates of transistors 84a and 84b. The voltages at nodes SA and SB are connected to the base at transistors 86a and 86b.

In the case where the line SSL goes high, the output of the inverter 82 goes low, and the output of the inverting delay stage 90 goes high logic level, thereby turning on the transistors 94a and 94b. However, as described above, the inverting delay stage 90 is configured to slow the low-to-high transition at the output. This delay caused by the delay stage 90 between the output of the inverter 82 and the gates of the transistors 94a and 94b begins to drive the data output lines 18_ and 18.

The turn-on delays of transistors 94a and 94b improve the access time, with the data state to be provided on data output lines 18 and 18_ being the same as the data provided on the data output lines within the previous read cycle. For example, if data output line 18 is driven to a high level with respect to data output line 18_ within a previous cycle by another second stage sense amplifier 14, transistor 86b is transistor 94b. While transistor 86b starts to drive data output line 18 before turning on, it maintains the same level as that on data output line 18 to provide a quick output response. When the transistor 94b is turned on before the transistor 86b is turned on, the data output line 18 is discharged to Vee, and the transistor 86b pulls the data output line 18 up to the output level, so that the SRAM 1 Slows down access time performance. Upon turn on by the inverting delay stage 90, the transistors 94a and 94b act as current sources to reflect the voltages of the data output lines 18 and 18_ to the differential voltages of the nodes SA and SB. The voltages provided to the data output lines 18_ and 18 are the voltages of the nodes SA and SB shifted by the base-emitter diode voltage drops of the transistors 86a and 86b.

In the example described above, when node SB is in a higher voltage state than node SA, data output line 18 is in a higher voltage state than data output line 18_. Therefore, the second stage sense amplifier 14 communicates the output of the selected first stage sense amplifier 10 to the input / output circuit 20 by sensing the data state of the selected memory cell 24.

In subsequent cycles in which the particular second stage sense amplifier 14 is not selected from the selected state, the line SSL goes to a low logic level, turning off the transistors 70, 72, 74, 84a and 84b and By turning on 92a and 92b, the bases of transistors 86a and 86b are pulled low. The inverting delay stage 90 turns off the transistors 94a and 94b quickly because the inverted delay stage 90 has a central fast response to the high-low transition in response to the output of the inverter 82. Because it is configured to let.

Therefore, the present invention described above groups the reduced number of first stage sense amplifiers 10 to drive a pair of local data lines 16 and 16_, and drives the global data output lines 18 and 18_. To provide a reduced load on the first stage sense amplifier 10 by having a second stage sense amplifier for each group selected by the most significant bit of the column address. The reduced drive provides a single first stage sense amplifier 10 for each column without requiring many drive transistors that cannot fit within the column pitch of the array.

As described above with respect to FIG. 4A, the bases of transistors 38a and 38b are biased to Vcc during the readout operation, whether or not a particular column is selected. The pull-up transistor 38 represents a diode between the bit line BL or BL_ and the voltage at the base of the transistor 38, respectively. The negative voltage bump on Vcc when the base of transistor 38 is connected to Vcc is due to the base-emitter diode of npn transistor 38 being reverse-biased when the base voltage drops below the bit line voltage. It is not coupled to the bit lines BL and BL_. However, if the power supply voltage Vcc bumps up, the bit lines BL and BL_ will follow the higher level of Vcc because the voltage across the base-emitter junction will maintain Vbe. During the decode operation, the low bit lines BL and BL_ are not pulled upwards by noise when the selected memory cell 24 remains low, but the bit lines that are high follow the positive polarity noise on Vcc. . Therefore, positive polarity noise on the Vcc power supply will produce a differential voltage between the bit lines that is greater than that present in the absence of such noise. If the noise is very loud, the bit line differential voltage can be large enough that the equalizing transistor 47 cannot equalize the bit line, making it impossible to sense the state of the selected memory cell 24 in subsequent cycles.

Referring to FIG. 9, another equivalent circuit diagram for the column of FIG. 3 in a decryption operation is shown, including another portion of the pull-up control circuit 23 associated with each pull-up transistor 38a and 38b. have. The portion of the pull-up control circuit 23 shown in FIG. 9 performs a low pass filter operation to filter the relatively high frequency noise in the Vcc power line by upsetting the equalization of the bit lines BL and BL_.

During the readout operation as described above with reference to FIG. 4A, one bit line of the bit line BL or BL_ goes high with respect to the other bit lines depending on the data state of the selected memory cell 24. In the example shown in FIG. 9, the bit line BL is high with respect to the bit line BL_.

The operation of the first stage sense amplifier 10 and the memory cell 24, including the selected transistor 45 operating as a current source and transistors 42a and 42b sharing a current through the transistor 45, is in a high state. It can be modeled as a first current source through the current I _HI coupled to the bit line BL and a second current source through the current I _LO coupled to the bit line BL_ in the low state, of course the opposite data state is selected. When stored in 24), equivalent current sources I _HI and I _LO are coupled to opposite bit lines BL and BL_. I _HI corresponds to the base current of transistor 42a in the example where bit line BL is high. I _LO corresponds to the current drawn from bit line BL_ (in this example) by memory cell 24 providing a low logic state.

To bias the base of the transistors 38a and 38b to Vcc, a lowpass filter consisting of a resistor 50 and a capacitor 52 is coupled to the pull-up control circuit 23. This lowpass filter biases nodes A and B for readout operation, but filters out high-frequency noise on the Vcc power supply, so positive polarity noise on Vcc passes through transistors 38a and 38b to bit lines BL and BL. _ Will not be reached. The values of the resistors 50 and capacitors 52 are slower than the response of the bit lines BL and BL_ to the voltage feedback through the equivalent current sources I _HI and I _LO at the maximum rate of change of the voltage at nodes A and B after the filter. Should be selected. Within this embodiment, resistor 50 has a value of 10 KHz and capacitor 52 is a MOS capacitor of 15-20 pF.

10 is a system diagram showing the configuration of the pull-up control circuit 23. As shown in FIG. The pull-up control circuit 23 includes two blocks 55a and 55b, each of which includes almost identical circuits therein.

Block 55a is for driving node A, which is the base of pull-up transistor 38a, and block 55b is for driving node B, which is the base of pull-up transistor 38b. Block 55a receives the input data input line 22 and the line INVB generated by block 55b, as described below. Similarly, block 55b receives data input line 22_ and line INVA generated by block 55a, as described below.

Referring to Fig. 11, block 55a is described in detail. Block 55b is similarly configured as described above. Data input line 22 is received by the input of blocks 55a and inverters 62 and 64 at the gate of n-channel transistor 60. Inverters 62 and 64 are CMOS inverters configured in known push-pull structures. The output of the inverter 62 is connected to the base of the n-p-n transistor 66, and the output of the inverter 64 is connected to the base of the n-p-n transistor 68.

Transistors 66 and 68 are connected biased by Vcc, with the emitter of transistor 66 driving the base of transistor 68. The emitter of transistor 68 is connected to the output of block 55a at node A. The combination of inverters 62 and 64, and the Darlington transistors 66 and 68, act as high speed pull-up circuits as described in US Patent Application No. 158,004 filed Feb. 16, 1988. This pull-up circuit, at node A, provides a logical maintenance of the state of the data input line 22.

On the pull-down side, the source-drain path of transistor 60 is connected in series to the source-drain path of n-channel transistor 70 between node A and Vee. The gate of transistor 70 is connected to node A. The junction between the transistors 60 and 70 is connected to the n-p-n transistor 72 in which the collector is connected to the node A and the emitter is connected to Vee. The pull-down circuits of transistors 60, 70 and 72 serve to quickly pull down node A when the logic state of data input line 22 is switched from a low logic level to a high logic level.

In addition, the output of the inverter 64 is connected to the first input of the NAND gate 74, the other input of the NAND gate 74 receives the line INVB from the block 55b of the pull-up control circuit 23. do. The output of inverter 62, via delay stage 63, provides a logic state on line INVA to block 55b in the pull-up control circuit. The line INVA is connected to the input of the NAND gate in the block 55b, which is arranged similarly to the NAND gate 74 in the block 55a, and the line INVB is the block (similar to the inverter 62 in the block 55a). Driven by an inverter in 55b).

These interconnects serve to cross-couple blocks 55a and 55b to control various read and write states as described below.

NAND gate 74 drives the gate of p-channel transistor 76, the gate of p-channel transistor 78, and the gate of small n-channel transistor 80. The source-drain path of transistor 76 is connected between Vcc and node A, and the source-drain path of transistor 78 is connected in series to filter resistor 50 between Vcc and node A. The source-drain path of transistor 80 is connected between node A and Vee. Also provided are diode-connected n-p-n transistors 82 and 84 together with the low pass filter of resistor 50 and capacitor 52. The collector and base of transistor 82 are connected to Vcc, the emitter is connected to the source of transistor 80, the collector of transistor 84 is connected to the source of transistor 80, and the base and emitter are connected to Vcc. do.

Thus, when transistor 78 is on during a decode operation (as described below), transistors 82 and 84 operate as counter diodes between Vcc and node A, resulting in a significant differential voltage between them. To prevent them.

In operation, block 55a acts to provide node A with the voltage described above with respect to FIGS. 4A and 4B, depending on the type of cycle performed by SRAM 1, as shown in FIG. Low pass filtering is provided during the decryption cycle as shown. As described above, during the read cycle, data input lines 22 and 22_ are both at a low logic level.

Regarding block 55a, line 22_ in the low state turns transistor 60 off, causing transistor 72 to turn off. Inverters 62 and 64 both provide high logic levels at their outputs, turning transistors 66 and 68 on. As described in patent application 158,004, the operation of transistors 66 and 68 in the form of multiarlington is bootstrapping from the parasitic junction capacitance of all Vcc levels, i.e., the base-emitter junction of transistor 68. It will start charging Node A quickly at all levels. In addition, the output of the inverter 64 provides a high level to the NAND gate 74, and the output of the inverter 62 provides a high level on the line INVA after a delay by the delay stage 63. .

In addition, because the data input line 22 is low and the block 55b is configured similarly to the block 55a, the line INVB from the block 55b is at a high level at the second input to the NAND gate 74. It becomes Therefore, the output of the NAND gate 76 goes low and turns on the p-channel transistors 76 and 78. Therefore, the p-channel transistor 76 helps pull-up of the Vcc low node A and allows node A to maintain this level until the output of the NAND gate 74 changes.

Transistor 78 acts to connect the low pass filter of resistor 50 and capacitor 52 to node A, as shown in FIG. 10, to filter out high frequency noise on the Vcc power supply line. As discussed above, diodes 82 and 84 limit the possible differential voltage between Vcc and node A while transistor 78 is on. Of course, transistor 80 is kept off during the readout cycle by the output of NAND gate 74. Since the connection of the resistor 50 to the node A and the capacitor 52 with the node A is gated by the transistor 78 in the block 55a, the filter circuit of the block 55a has a large number of pull-up control blocks in the SRAM (l). May be shared by block 55b or ancillary blocks 55a and 55b when provided for other bit line pairs. This sharing can be achieved by connecting a node at the source of transistor 78 to a source of similarly arranged transistors in another block.

During a write cycle in which the bit line BL is low level, that is, the data line 22_ is high level as shown in FIG. 3, node A is biased to Vee. The circuit of block 55a shown in FIG. 1L achieves this by turning on the transistor 60 with the data input line 22_ going to a high level. Transistors 70 and 72 are turned on by turning on transistor 60 when node A is initially at a high level, so node A can be quickly discharged through bipolar transistor 72. Incidentally, the outputs of inverters 62 and 64 go low, turning transistors 66 and 68 off and turning transistors 76 and 78 through NAND gate 74. Small transistor 80 is turned on. Thus, node A is pulled to Vee by block 55a when data input line 22_ goes high, which causes the bit line BL associated with transistor 38a (driven by node A) to write operation. Means to take a low state. The output of inverter 62 is communicated to the input of the NAND gate in block 55b similar to NAND gate 74 to achieve the bias of Node B in a manner as described below for block 55a.

During a write cycle in which the bit line BL_ is low, that is, the data line 22 is at a high level, node A is biased to Vcc-Vbe in accordance with the present invention, as described above with reference to FIG. 4b. In this case, data input line 22_ is turned low, turning on transistors 66 and 68, and turning off transistors 60, 70 and 72 as in the case of the readout cycle described above. . However, since data input line 22 is at a high level, block 55b provides a low logic level on line INVB to the second input of NAND gate 74, because the inverter in block 55a ( This is because the inverter in the block 55b arranged similarly to 62 will have a low output due to the data input line 22 at the high logic level. Thus, within block 55a, the output of NAND gate 74 is at a high level (one of the inputs is at a low level), thus turning off transistors 76 and 78, but turning transistor 80 off. When turned on, node A is coupled to Vee.

However, as described above, the transistor 80 is a relatively small transistor, resulting in a resistive load on the pair of Darlington transistors 66 and 68. This resistive load causes the circuits of transistor 68 and transistor 80 having node A at the junction to act as emitter follower.

After attenuation of some bootstrapping at the base of transistor 68, the base of transistor 68 is at the Vcc potential driven by CMOS inverter 64. Thus, the emitter of transistor 68 at node A is at Vcc-Vbe due to transistor 80 acting as a pull-down load. Therefore, block 55a operates to bias the base of transistor 38a in node A, i.e., Figure 4b, to a voltage of Vcc-Vbe that is lower than the voltage that node A is biased during the read cycle. Thus, the intersection reaches an early time when the decryption cycle is started after the write operation as shown in FIG.

The delay of the delay stage 63 is used to cause the intersection of the bit lines BL and BL_ to occur during the read cycle following the write cycle. The delay provided on line INVB to block 55a (and vice versa, line INVA to block 55b) is such that pull-up transistor 38 associated with p-channel transistors 76 and 78 is driven to Vcc-Vbe. During the data state, it is kept off after the write cycle. For example, a block (configured similar to block 55a)

If 55a biases node A to Vcc-Vbe during the write cycle, and returns line 22 to a low state to mean readout, block transistors 76 and 78 remain off, It is preferable to prevent the node A from being immediately pulled from Vcc-Vbe to the entire Vcc level during the period in which the bit line BL_ is charged in the decryption operation. As shown in FIG. 5, when node A becomes Vcc before node B, the bit line BL can reach the final level at an early time after t _r . However, the early intersection point according to the invention is due to the voltage of the bit line BL which is in the lower voltage state (if shown) during the write cycle than during the readout, thus causing the intersection point to occur while the bit lines BL and BL_ are charged. The intersection at time t _s is delayed if it occurs after the bit line BL is fully charged to the final level by the memory cell 24. The longer the delay, the lower the voltage on the bit line BL at the crossing point, and therefore, it is known that the bit line BL_ reaches the voltage of the bit line BL.

Of course, the delay amount of the delay stage 63 is a data state in which the delay is opposite to that shown in FIG. 5, where the bit line BL is maintained at Vcc-2Vbe after the bit line BL_ is charged to the zero sensing level. In case of decryption, it cannot be enough to cause a false intersection. The delay of delay stage 63 may be achieved in a number of ways other than those shown in FIG. 11, such as selectively inducing a signal from node A.

As described herein, block 55a may operate to control the bias of pull-up transistor 38a for all 1024 columns in SRAM 1 and block 55b may operate in all of SRAM 1. 1024 columns can be operated to control the bias of the pull-up transistor 38b. Optionally, 1024 rows can be divided into column groups, with each pair of blocks provided with a pair of blocks 55a and 55b. In the case where a plurality of blocks 55a and 55b are provided, each providing only one column group in the SRAM 1, selectively disabling all blocks 55a and 55b except the pair associated with the column group containing the selected column. In order to do so, decoding and selection circuitry may be provided within each block 55a and 55b.

As described above, the present invention provides a pull-up control circuit that not only improves data storage reliability in a memory device but also improves performance. The Vcc power supply provides increased reliability to the memory device in a noisy environment, which is enhanced by a filter included in the pull-up control circuit 23. Improved performance is provided to improve the read access time in the cycle following the write operation by a pull-up control circuit that biases the pull-up transistor in the write cycle to a lower voltage during the read cycle.

The embodiment described above also relates to an architecture where each column has its own first stage sense amplifier. The advantages of the present invention of reducing the impact of power supply noise on the bit line voltage and biasing the bit line during a write operation to provide improved write recovery can be applied to an architecture where multiple columns share a single sense amplifier. .

While the present invention has been described in detail with reference to preferred embodiments of the present invention, this description is merely an example and should not be construed in a limiting sense. In addition, those skilled in the art can change the embodiments of the present invention in various forms. Such changes and incidental embodiments are limited only by the scope of the appended claims.

Claims (10)

An address buffer for receiving a memory cell array address signal arranged in rows and columns, a row decoder connected to the address buffer to select a row of the array in response to a row address portion of the address signal, a first group and a second A plurality of first stage sense amplifiers grouped into groups, each associated with a column of the array, a first local data bus connected to each of the first stage sense amplifiers in the first group, each of the above in the second group A second local data bus connected to a first stage sense amplifier, a data output bus, a first second stage sense amplifier connected to the first local data bus and the data output bus, the second local data bus and the data; Selecting a second stage sense amplifier connected to an output bus and a first stage sense amplifier in response to a column address portion of the address signal, Column decode means connected to an address buffer for selecting a second stage sense amplifier to provide an output of the selected first stage sense amplifier on a data output bus in response to the column address portion of the address signal, And a second stage sense amplifier in response to at least one bit of bits in the column address portion of the address signal used when the column decoder means selects the first stage sense amplifier. . 2. The second thermal decoder of claim 1, wherein the column decode means receives a predetermined number of most significant bits of the column address portion of the address signal from the address buffer and, in response, selects a second stage sense amplifier; And a column address portion of the address signal from the address buffer that includes a predetermined number of most significant bits of the column address portion of the address signal received by the second thermal decoder and, in response, receives the first stage sense amplifier. And a first stage decoder for selecting. Has an array of memory cells arranged in columns and rows, each associated with a pair of true and complementary bit lines, has an address buffer for receiving an address signal, and selects a row of the array in response to a row address portion of the address signal A read / write memory of a type having a row decoder connected to an address buffer for supplying a row, and having a column decoder for selecting a column of an array in response to a column address portion of an address signal, the first group and the second group. A plurality of first stage sense amplifiers, grouped together, each connected to a true and complementary bit line associated with a column of the array, each of the first stage sense amplifiers connected to each of the first stage sense amplifiers in the first and second groups. A second local data bus, a data output bus, a first second stage sense amplifier connected to the first local data bus and the data output bus, and A second second stage sense amplifier connected to a second local data bus and the data output bus, wherein the column decoder selects a first stage sense amplifier in response to a column address portion of the address signal; Selecting a second stage sense amplifier in response to a predetermined number of most significant bits of the column address portion of the address signal used to select the first stage sense amplifier, such that the selected second stage sense amplifier is associated with a selected column of true and complementary bit lines. And providing a voltage on the data output bus corresponding to the polarity of the differential voltage of. 4. The second thermal decoder of claim 3, wherein the column decoder receives a predetermined number of most significant bits of the column address portion of the address signal from the address buffer and, in response, selects a second stage sense amplifier; Receive a column address portion of the address signal from the address buffer including a predetermined number of most significant bits of the column address portion of the address signal received by the second thermal decoder and select a first stage sense amplifier in response thereto A read / write memory comprising: a first stage decoder for An array of memory cells arranged in rows and columns; A row decoder for receiving a row address signal and in response selecting a row in the array of memory cells; And a column decoder for receiving a column address signal and in response to selecting a column in the array of memory cells, providing data of the memory cell in the selected column in the selected row during a read operation, and writing A read / write memory device operable to write input data to a memory cell in a selected column within a selected row during operation, wherein each column of memory cells in the array shares true and complementary bit lines. A sense amplifier in communication with a bit line of a column of the array selected by the column decoder to sense data stored in a memory cell in the selected column in the response, response to input data in a first logical state during a write operation Bypass the true bit line in the selected column with the A write circuit for biasing complementary bit lines in a selected column with said predetermined voltage in response to input data in a second logical state during a write operation, an emitter connected to an associated true bit line, said power supply A first pull-up transistor for each true bit line in each column having a collector connected to a supply node, a base, an emitter connected to an associated complementary bit line, the power supply node A second pull-up transistor for each complementary bit line in each column having a collector connected to the base and a pull-up control circuit connected to the bases of the first and second pull-up transistors; Wherein the first and second pull-up transistors are biased in an on state during a read operation and, in a write operation, according to the logic state of the input data, 1. The read / write memory device of claim 1, wherein one of the first or second pull-up transistors is biased to a voltage lower than the on state of the read operation and the other transistor is biased off. 6. The write circuit of claim 5, wherein the write circuit biases the true bit line in the selected row to a low voltage in response to input data in a first logical state during a write operation, and input data in a second logical state during a write operation. And decipher the complementary bit line at a low voltage in response to the read / write memory device. The voltage of claim 6, wherein the pull-up control circuit biases the first pull-up transistor in the selected column and is lower than an on state in a read operation in response to input data in the first logical state. Biasing a second pull-up transistor in the selected column, wherein the pull-up control circuit biases off the second pull-up transistor in the selected column and in response to input data in the second logical state. And reading the first pull-up transistor in the selected column at a voltage lower than the on state of the read operation. 6. The first and second pull-up transistors in unselected columns of claim 5, wherein the pull-up control circuit is biased to a voltage lower than the on state in a read operation, in accordance with the logic state of the input data. Deciphering one of the transistors and biasing off the other transistor. An array of memory cells arranged in rows and columns; A row decoder for receiving a row address signal and in response selecting a row in the array of memory cells; And a column decoder for receiving a column address signal and in response to selecting a column in the array of memory cells; Sensing and output circuitry for providing data of memory cells in a selected column in a selected row during a read operation; And a write circuit for writing input data to a memory cell in a selected column in a selected row during a write operation, wherein each column of memory cells in the array shares true and complementary bit lines. A first pull-up transistor for each true bit line in each column having an emitter connected to an associated true bit line, a collector connected to the power supply node, and a base; A second pull-up transistor for each complementary bit line in each column having an emitter connected to an associated complementary bit line, a collector connected to the power supply node, and a base; And a pull-up control circuit connected to a base of the first and second pull-up transistors, wherein the pull-up control circuit is biased with the first and second pull-up transistors turned on in a read operation. And a bias circuit connected to said base of said first and second pull-up transistors, and a low pass filter connected between said power supply node and said base of said first and second pull-up transistors. A read / write memory device characterized by the above. An array of memory cells arranged in rows and columns; A row decoder for receiving a row address signal and in response selecting a row in the array of memory cells; And a column decoder for receiving a column address signal and in response to selecting a column in the array of memory cells, providing data of the memory cell in the selected column in the selected row during a read operation, A read / write memory device operable to write input data to memory cells in a selected column in a selected row during a write operation, wherein each column of memory cells in the array shares true and complementary bit lines. A sense amplifier in communication with a bit line of a column of the array selected by the column decoder to sense data stored in a memory cell in the selected column in a row, to input data in a first logical state during a write operation. In response a true bit line in a selected column with the predetermined voltage A write circuit for biasing and biasing complementary bit lines in a selected column with a predetermined voltage in response to input data in a second logic state during a write operation, an emitter connected to an associated true bit line, said power supply node A first pull-up transistor for each true bit line in each column having a base, an emitter connected to an associated complementary bit line, a collector connected to the power supply node, and a base connected to the collector; A second pull-up transistor for each complementary bit line in each column having a pull-up control circuit connected to bases of the first and second pull-up transistors; The pull-up transistor is biased to an on state in a read operation and, in a write operation, according to the logic state of the input data, the first in a selected column Is one of the second pull-up transistors biased to a voltage lower than the on state in the read operation, the other transistor is biased off, and the pull-up control circuitry receives data for receiving the first data input signal. The first pull-up having an input, a feedback input, a delayed feedback output for providing a delay signal in response to a logic state of the data input signal, and a bias output connected to the base of the first pull-up transistor A first input for biasing the base of the up transistor and a data input for receiving a second data input signal, a feedback input coupled to the feedback output of the first block, and a second input input signal for Has a feedback output connected to the feedback input of the first block to provide a delay signal in response to a logic state, And a second block for biasing the base of the second pull-up transistor having a bias output coupled to the base of the second pull-up transistor.

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