KR970004790B1 - The channel multiplex apparatus of the fiber loop carrier - Google Patents

Abstract

The present invention relates to a channel multiplex system for a fiber loop carrier. The inventive channel multiplex system includes a power supply unit (PSU) receiving -48V and converting it to a voltage required for each unit and supplying the same; 30 channel units (CU) receiving power from the PSU, and performing selectively read/write operation from/into four couples of digital first group velocity PCM buses in response to an internal transmitted/received clock and timing signal; a pulse code modulation (PCM) bus including four pairs of PCM signal connection lines coupled to the CUs and a pair of control signal connection lines; a clock and concentration unit (CCU) controlling the transfer speed of the PCM bus, processing signal processing related information and maintenance & compensation information, and performing time slot switching function; a frame interface unit (FIU) forming a digital first group velocity frame; a bank control unit (BCU) controlling the overall parts and providing an interface with an operator; and a bank management unit (BMU) holding the operation and maintenance data of the above units.

Description

Channel Multiplexer of Optical Subscriber Transmitter

1 is a schematic diagram for explaining a connection state between channel multiplexing apparatus according to the present invention.

2 is a block diagram showing the configuration of the PCM bus of the channel multiplexing apparatus according to the present invention.

3 is a perspective view of a channel multiplexing apparatus according to the present invention.

* Explanation of symbols for main parts of the drawings

10: power supply unit (PSU) 20: channel unit (CU)

30: PCM bus 40: clock supply and concentrator (CCU)

50: frame interface unit (FIU) 60: bank control unit (BCU)

70: Bank Management Unit (BMU) 80: Enclosure

82: guide rail 84: serial port

86: Test Project

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel multiplexing device of a fiber loop carrier (FLC), and in particular, a channel unit capable of receiving four voice frequency (hereinafter referred to as VF) subscriber level signals. Up to 120 lines per channel multiplexer with 30 channels per channel multiplexer, each channel being selectively connected to four pairs of pulse code modulation (PCM) buses. Time division multiplexing and demultiplexing of VF-level signals and digital data signals into four digital first-order signals according to PCM A law, and interworking with synchronous transmission equipment through 2048kbps interface and effectively arranging each component to improve reliability of device operation The present invention relates to a channel multiplexing apparatus that can be enabled.

In general, there are synchronous transmission and asynchronous transmission for multiplexing the VF-level digital signal of the dependent signal 64kbps and the basic access signal of the integrated service digital network (hereinafter referred to as ISDN).

Currently, in the process of transitioning from the existing asynchronous transmission method to the synchronous transmission method for maintenance and provision of new services, it is expected that the asynchronous transmission method will coexist for a long time. There is a need to accommodate these two different transmission methods as a single communication device and to accommodate as many subscriber lines as possible.

The general synchronous transmission method is as follows.

First, dependent signals of the optical subscriber network include 64kbps, 1544kbps, 2048kbps, and 44736kbps signals, and each dependent signal is changed from a bipolar signal to a unipolar signal according to the multiplexing level, and then synchronous VC through a container signal. It is converted into a virtual container signal, and in this process, the difference between the VC signal speed and the system clock is controlled by adjusting the positive and negative frequencies. The VC signal is converted into an upper VC signal through the TU and TUG signal stages or forms an STM-1 signal through the AU and AUG signal stages.

In the channel multiplexer, PCM-encoded VF band signals or 64kbps digital signals are first multiplexed in the channel bank and converted into DS1 (1544kbps), which is North American primary speed, or DSIE (2048kbps), which is European primary speed, and then synchronous multiplexing. Depending on the structure, it is converted to a VC11 or VC12 signal through floating asynchronous or floating byte synchronization.

Here, the conventional channel multiplexing apparatus will be described.

That is, one channel multiplexer is divided into four blocks, and each block is composed of the same device. Each block has 12 CUs that can accommodate one or two VF-class signals on one side of the channel multiplexer block, and control and connecting devices are installed in each block. The control and connection devices include a power supply unit (hereinafter referred to as PSU), a clock and concentration unit (hereinafter referred to as CCU) and a frame interface (hereinafter referred to as FIU). It consists of a bank contral unit (hereinafter referred to as BCU) and a bank management unit (hereinafter referred to as BMU), each CU and CCU having four pairs of data transfer PCM buses and one pair of control PCMs. It is connected by bus.

In the channel multiplexing device, the control devices are arranged at the center and the respective CUs are arranged at both sides.

However, in the above CUs, one channel is connected to one PCM bus, so connection with other buses is impossible, and up to 4 (blocks) x 12 (CU) x 2 (line) 4 VF-class subscribers are provided by one device. = 96 lines can be accommodated.

Therefore, the conventional channel multiplexing device requires four control and connection devices other than the CU, which makes it difficult to increase the line size in the limited enclosure space, and increases the use line because the channels cannot be interconnected between blocks within a device.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a subscriber transmission network between a central office terminal (hereinafter referred to as a COT) and a remote terminal (hereinafter referred to as RT). A part of FLC which multiplexes a large number of subscriber lines in synchronous optical transmission, and multiplexes subscriber signals such as VF-class signals, digital data signals or ISDN basic access signals at digital primary group speed or from digital primary group speed. In order to demultiplex to subscriber line, 30 CUs are installed per device. In one CU, 4 pairs of 64kbps subscriber signals and 2 digital data signals or 2 ISDN (2B + D) subscriber signals are selectively selected. In the case of VF class, it is connected with PCM bus and can provide up to 120 lines per device.

Another object of the present invention is to provide a channel multiplexing apparatus capable of selecting and operating a digital primary group speed interface synchronously or asynchronously.

Still another object of the present invention is to arrange 15 CUs up and down in the inner center of the hollow rectangular body-shaped channel multiplexing unit, and install two PSUs on one side in a row, and on the other side, a signal control and processing device. By minimizing the interference between power supply noise, VF signal, PCM signal and device control signal, the reliability of device operation can be improved, and the channel multiplexing device can increase the acceptance line.

A feature of the channel multiplexing apparatus according to the present invention for achieving the above object is that two PSUs are supplied with -48V, converted to the required voltage in each unit, and PCM-encoded VF-class signals of four lines. Digital data of one line and ISDN (2B + D) signals of two lines are temporarily stored in memory and selectively read / written to four pairs of digital primary speed PCM buses within the device according to internal transmit / receive clock and timing signals. PCM bus consisting of 30 CUs, four pairs of PCM signal connection lines and one pair of control signal connection lines connected to the CUs, and control the transmission speed and clock phase of the PCM bus. Digital primary group speed by receiving two pairs of CCU which processes signal processing related information and maintenance information and performs timeslot switching function and digital signal on the internal PCM bus. Two FIUs that compose and transmit frames to and from the outside of the device, a BCU that collectively controls the devices and provides an interface with the operator, and stores and maintains operation maintenance data of the devices and can test the subscriber line. It is provided with a BMU having the terminals on the front.

In addition, a feature of the channel multiplexing apparatus according to the present invention for achieving another object is a hollow rectangular shape, which can be equipped with a vertical 3U and 6U size circuit unit, and is installed on one side of the housing required for each circuit PSU supplies + 5V, -5V, + 12V, -12V, ring signal, etc., and supplies + 5V only to common unit, and is arranged in two columns above and below one side of the PSU to receive DSO level signals for multiplexing or time slot assignment. Afterwards, the most lossy CUs sending DSIE-class PCM signals, the CCUs installed on the other side of the CUs to control the PCM bus, and the DSCU-class PCM signals installed on the other side of the CCU to transmit to the outside. A BCU for minimizing pattern interference between a control signal, a PCM signal, and a VF signal that causes noise on the other side of the FIU, the PCM signal flow is completed, and controlling the channel multiplexer as a whole; Is installed on the other side of the group receiving BCU periodically back up the data of the BCU, it is as provided by a test pattern associated with each CU provided with a BMU so as to enable a self-test to facilitate the backboard pattern design.

Hereinafter, a channel multiplexing apparatus of an optical subscriber transmission apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

1 and 2 are views for explaining a channel multiplexing apparatus of the FLC according to the present invention, and will be described in relation to each other.

First, the channel multiplexing apparatus of the FLC according to the present invention is connected to two PCUs 10 and 4 subscriber lines which supply power as a whole, and encodes a PCM bus 30 by encoding VF signals according to the European PC MA law. PCM bus 30 comprising four pairs of signal connection signal lines and one pair of control signal connection lines connected to 30 CUs 20 to select and read / write, and transmission speed of the PCM bus 30 And two CCUs 40 for adjusting a clock phase and processing signal processing and maintenance information of each line, and a constant digital primary group speed signal for transmitting a signal of the PCM bus 30 to the outside of the FLC. Two FIUs 50 forming a frame and transmitting to the outside of the device, the BCU 60 having the overall control of the channel multiplexing device and the operator control function, and the maintenance data of the CU 10 are stored and joined. With the test function of the line It consists of a BMU (70).

Looking at the operation of each of the components in more detail as follows.

First, the PSU 10 receives -48V from the power distribution panel and converts the voltage to ± 5V and ± 12V, which are required by each device, and supplies a ring signal to each CU 20 from an operating self. The PSU 10 is duplicated and connected in parallel so that if one fails due to an unstable power supply or the like, the PSU 10 operates normally with only one other device. In addition, since the ring signal is supplied through the fuse, only one device is blocked even in the event of a lightning strike of one device and the entire FLC system is not affected.

In addition, the CU 20 is installed in a single device in a total of 30 up to 15, can be classified into a VF class and a data class, each of the four 64kbps VF-class circuit, two data or ISDN-class circuit Can accommodate The VF-class CU 20 performs the functions of PCM code, subscriber line interface, subscriber signal monitoring, and timeslot access, and the data-class CU 20 includes OCUDP and DSODP, and has 2.4, 4.8, 9.6, and 56kbps signals. Can be accommodated selectively, and there is an error correction function.

In addition, the PCM bus 30 is a data transmission path between the CUs 20, the CCU 40, and the FIU 50. The PCM bus 30 includes four pairs of PCM signal transmission buses and one pair of device control buses. The data transfer rate is 2048kbps. Each CU 20 is connected to four pairs of PCM signal transmission buses and a pair of device control buses, and each CU 20 has a bus selection function so that each CU 10 selectively selects a PCM signal. It is connected to the PCM bus 30 for transmission.

The device control PCM bus 30 is a time slot 1-15 and 17-30 of the PCM basic frame consisting of 32 timeslots numbered from 0 to 31 times up to 4 times in the 30 CU (20) By assigning slots, the timeslot 16 is allocated to the CCU 40 or the FIU 50, and the timeslot 0 is used for frame synchronization. The PCM bus 30 is paired upstream and downstream, respectively, and accesses any PCM bus line in the CUs 20. Operation maintenance data between the CCU 40 and the FIU 50 and the respective CUs 20 are transmitted through the control bus of the PCM bus 30.

The signal processing flow of such a device is as follows. First, the VF signal input to the VF-class CU 10 is sampled at 8 kHz by an A / D converter (not shown), and then converted into a digital signal according to the PCM A law to specify a designated time. Multiplexed into slots, the digital signal inputted to the digital data or the ISDN CU 11 undergoes error correction rate conversion without A / D conversion, and then multiplexed into a designated timeslot. The digital primary group speed multiplexing subscriber channel is assigned to a time slot on the PCM basic frame. The primary frame of the North American type primary speed has 24 time slots for two system channels and 20 subscriber 64 kbps signal channels. Accept.

In the present invention, the 120-channel multiplexing apparatus multiplexes the VF-class 120 subscriber channels into four primary European primary frame rate frames and transmits them to the synchronous multiplexer according to the synchronous multiplexing hierarchy.

In addition, the CCU 40 includes a time slot processing logic and a clock processing circuit for controlling the PCM bus 30 between the functional blocks, and has a switching function for the 2: 1 condensing function of the PCM bus 30. In addition, signals generated in each CU 20 are transmitted to the four PCM buses 30 in accordance with the timing of the CCU 40, and in this process, signals are transmitted between the CU 20 and the CCU 40 in arbitrary timeslots. It also has a time slot assignment and bus select function, which switches the timeslot on the PCM signal in timeslot memory when channel switching is required. The CCU 40 is a pair is connected in parallel, even if a failure occurs in one, the other one operates normally.

In addition, the FIU 50 forms a constant digital primary group speed signal frame to transmit the signals read / written to the PCM bus 30 to the outside of the channel multiplexer, and in addition to the subscriber signal, the operation maintenance data and the signaling method signal. Add The signal frame may transmit the synchronous transmission hierarchy without line code conversion in accordance with the synchronous clock, transmit the asynchronous transmission hierarchy after the HDB3 line encoding, or selectively transmit the asynchronous hierarchy after the HDB3 transmission line encoding. The FIU 50 accommodates two DSIE signal frames per one.

In addition, the BCU 60 is a device for overall control of the channel multiplexing device. The BCU 60 is connected to a terminal through system initialization, register initial value setting of each function block, communication between devices using an operation maintenance channel, and a serial port attached to the front of the device. Can be controlled by the operator.

In addition, the BMU 70 stores and maintains the channel maintenance data, and provides a test function for a subscription line through a test jack attached to the front side. For the channel test, the CU 30 has a test relay, which is driven by a test selection terminal of the BMU 70, a command of a terminal and an operating self connected to the BCU 60, or a remote test command.

3 is a perspective view of a channel multiplexing apparatus according to the present invention.

First, the hollow hollow rectangular housing 80 is a structure on which PCBs are mounted, and a main board (not shown) on which a board connector and wiring are formed is installed, and a guide rail having an H shape ( 82), and various parts such as the front plate 84 are installed therein.

The enclosure 80 is standardized by international organizations such as the International Electrotechnical Commission (IEC) and the Electronics Industries Association (EIA), and the enclosure 80 is applied to a channel multiplexing apparatus according to international standards. The first can be 23 inches wide and 6U high (265.9mm), allowing a 3U high PCB.

The capacity of the channel multiplexing device is assumed to be 250W maximum output that the housing 80 of 23 inches × 6U can be provided in a closed space, and VF-class 120 subscribers in consideration of the multiplexing and 2: 1 converging function, etc. Designed as 4E1 class. The channel capacity per device is designed to accommodate two telephone four-line special services on a 3U high PCB.

In the case of related existing equipment, there are many cases where two lines are mounted at the height of 3U, and in the FLC channel multiplexing apparatus of the present invention, it is assumed that the space required for the passive device for the external interface is used as the existing equipment, and the logic and signal processing are separate. Instead of the device, a highly integrated IC is used to accommodate up to four VF-class lines. If the number of circuits is increased further, the codec function and the line interface function should be installed more densely. Therefore, it is difficult to secure de-producibility and reliability in signal processing and line interface. It is not easy to handle a large amount of communication lines connected to the back side.

The functional elements of the channel multiplexing device were arranged in accordance with the functional system and enclosure structure, and the function of the device was adjusted and arranged.

First, the channel multiplexing device is divided into a common device with the CU 20 in terms of function, and the CU 20 includes a line connection function, a signaling method function, and a codec function suitable for various services, and the common device is multiplexed and clocked. It is divided into supply, device control, communication function with other devices, and power supply.

DSOs in 30 total CUs (15) up and down on the left side of the CCU (40) controlling the PCM bus in the channel multiplexer in the signal flow and the circuit layout design, which are the most important in the structural design of the channel multiplexer. After receiving the signal and assigning multiplexing or timeslot, the interference of the signal is minimized by sending out the DSIE signal from the FIU 50 installed on the right side of the CCU 40.

In addition, the BCU 60 for overall control of the channel multiplexing device is located on the right side of the FIU 50 after the signal flow, rather than being located in the middle of the signal flow between the CU 20 and the FIU 50, which is a DSIE frame component, a control signal, Interference between PCM signal and VF signal was minimized, and serial port 84 was installed on the front so that the operator could be controlled through the terminal. In addition, the BMU 70 is located on the right side of the BCU 60 to periodically back up the data of the BCU 60, and extends a test pattern commonly connected to the circuit test relays of each CU 20 to enable self-testing. The self-rear was connected to the operating self through the connector, and the test project 86 was installed at the front to test the circuit.

In addition, the PSU 10 is installed on the far left side, that is, on the left side of the CU 20 with the most power loss, and supplies + 5V, -5V, + 12V, -12V, and ring signals, and then supplies only + 5V to the common device. Arranged to facilitate the pattern design. The location of the power supply unit is generally located next to the function that consumes the most power in the device or to supply current to the outside. In the case of the channel multiplexer, the subscriber line interface has a larger current drive function than the control unit and the E1 interface. CU 20 was placed sideways immediately.

As described above, the FLC channel multiplexing apparatus according to the present invention arranges 30 CUs in the center of the enclosure, installs a central processing unit CCU, FIU, BCU and BMU on one side, and installs a PSU on the other side. Since the CU is equipped with a total of 30 CUs connecting four VF-class or two data-class lines in one device, up to 120 lines can be accommodated per device, and four 2048kbps signal frames multiplexed with subscriber signals are coded. It is possible to transmit to the synchronous transmission hierarchy according to the synchronous clock without conversion or to the asynchronous hierarchy after passing the HDB3 line encoding.

In addition, the channel multiplexing device is arranged inside the enclosure in the order of PSU, CU, CCU, FIU, BCU, and BMU to minimize interference between power noise, VF signal, PCM signal, and device control signal, and to install many lines in a limited space. There is another advantage that can be accommodated with ease.

Claims (10)

A PSU that receives -48V and converts it into a voltage required by each unit, and receives power from the PSU, PCM-encodes four VF signals, or digital data of two lines and ISDN of two lines. 2B + D) 30 CUs temporarily stored in memory and selectively read / write to 4 pairs of digital primary speed PCM buses in the device according to the internal transmit / receive clock and timing signals. PCM bus, consisting of four pairs of PCM signal connection and one pair of control signal connection, adjusts the transmission speed and clock phase of the PCM bus and processes signal processing and maintenance information of each line. A CCU performing a slot switching function, a FIU configured to receive a digital signal on the internal PCM bus, respectively, and to configure a digital primary group speed frame, and to transmit and receive to the outside of the device; The general control device and channel multiplexing apparatus having a BCU and, more BMU to store the operation data of the maintenance unit that provides an interface with the operator. 2. The channel multiplexing apparatus of claim 1, wherein the PSU is duplexed so that the channel multiplexing device operates normally even when the PSU malfunctions due to voltage instability. The channel multiplexing apparatus of claim 1, wherein the CU has a channel test relay on its front surface to perform a channel test function. 2. The channel multiplexing apparatus of claim 1, wherein the PCM bus transmits data at a rate of 2048 kbps. The channel multiplexing apparatus of claim 1, wherein the CCU is duplexed so that if one malfunctions, the channel multiplexing device operates normally. The method of claim 1, wherein the FIU combines the multiplexed signals on the PCM bus to form a European primary rate frame, and adds four operation multiplexed by adding operation maintenance data and signaling signal transmission data in addition to the subscriber channel. The 2048kbps signal frame is transmitted to the synchronous transmission layer according to the synchronous clock without code conversion or after HDB3 line encoding, and then to the asynchronous hierarchy and receives two DSIE signals per device. Multiplexer. It is a hollow rectangular shape that can be equipped with 3U and 6U sized circuit boards, and installed on one side of the enclosure to supply + 5V, -5V, + 12V, -12V, ring signals, etc. required for each circuit. In the common unit, the PSU supplying only + 5V, and the top and bottom two columns arranged on one side of the PSU, the CUs with the most power loss to receive the DSO-level signal and assign the DSIE-class PCM signal after multiplexing or time slot assignment, A CCU installed on the other side of the CUs to control a PCM bus, a FIU installed on the other side of the CCU to receive the DSIE-class PCM signal, and transmitted to the outside; and a cause of noise generation on the other side of the FIU where the PCM signal flow is completed Minimized pattern interference between control signals, PCM signals, and VF signals, and a BCU that collectively controls the channel multiplexing device, and is installed on the other side of the BCU to periodically back up data of the BCU, An optical channel multiplex transmission apparatus of the subscriber device with a BMU connected one by having the test pattern to enable a self-test. 8. The channel multiplexing apparatus of claim 7, wherein an H-shaped guide rail for supporting the housing is provided on the front surface of the housing. 8. The apparatus of claim 7, wherein the front panel of the BCU has a serial port connected to the outside to control the operator. The apparatus of claim 7, wherein the BMU performs a test on a subscription line through a test jack attached to a front surface of the BMU.