KR970004347B1 - Signal delay circuit and address transition detecting circuit of static ram using the delay circuit - Google Patents

Abstract

Address transit detecting circuit of static RAM(SRAM) is made up of the NOR gate(5) that receives address and chip-enable signal(CEX), the delay circuit(61) which delays the output of delay circuit and NOR gate, which inverts the output of the XOR gate to operate exclusive-or logic process, the delay controller which is made up of the first and second standard voltage generating circuit(91,92) to supply standard voltage to control delay time by connect to delay circuit, and the first and second switching means(62,63). The output of XOR gate switches the first standard voltage generating circuit, the output of inverter which inverts the output of XOR gate switches the second standard voltage generating circuit.

Description

Signal Delay Circuit and Address Transition Detection (ATD) Circuit of Static RAM

1 is a circuit diagram showing the configuration of the ATD circuit of the SRAM,

2 is a circuit diagram showing the configuration of a delay circuit;

3 is a view for explaining the operation of the delay circuit of FIG.

4 is a circuit diagram of a first embodiment of a delay circuit according to the present invention;

5 is a graph showing the operating characteristics of the reference voltage generating circuit constructed in the circuit of the present invention;

6 is a circuit diagram of a second embodiment of a delay circuit according to the present invention;

7 is a circuit block diagram showing the configuration of the ATD circuit of the SRAM constructed by adopting the delay circuit of the present invention;

FIG. 8 is a circuit diagram embodied in the block diagram of FIG.

9 is a timing diagram for explaining an operation state of the circuit of the invention of FIG. 8;

FIG. 10 is a timing diagram for explaining an operation state of the circuit of the invention of FIG.

* Description of the symbols for the main parts of the drawings *

1,5 NOR gate 2: delay circuit

3,7: XOR gate 4,8: Inverter

9: reference voltage circuit section 91: first reference voltage generating circuit

92: second reference voltage generating circuit 61: delay circuit

62: first switching means 63: second switching means

64: transmission gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal delay circuit and an address transition detection (ATD) circuit on a static RAM using the same. In particular, the present invention stably outputs an input signal with a constant delay even when a power supply voltage is changed (3V to 5V). A signal delay circuit and an address transition detection (ATD) circuit of a static RAM (SRAM) using the same are provided.

In general, in designing a circuit, it is often necessary to configure a delay circuit that outputs a specific signal after delaying a predetermined signal for a predetermined time due to matching of signals or matching of propagation time.

Particularly, among the stack memory semiconductors (hereinafter, referred to as SRAMs), which do not have a refresh operation and have an advantage of easy timing as a memory, unlike a dynamic RAM (DRAM) among the semiconductor memory devices, an internal clock pulse is not inputted externally. An asynchronous SRAM operated by generating a clock has an address transition detector (hereinafter referred to as ATD) for generating a clock internally.

The operation characteristic of the ATD is to generate a pulse by detecting a change in an address signal input from the outside, and the configuration thereof is as shown in FIG.

A NOR gate 1 that receives a chip enable signal CEX, which is an externally input address signal ADDI, is output by performing an NOR operation, and outputs the NOR gate 1 by delaying a predetermined time. A delay circuit 2, an XOR gate 3 for receiving an output signal of the delay circuit 2 and an output signal of the NOR gate 1, and outputting the calculated value after an exclusive OR operation; 3) It consists of an inverter (4) that receives the output and inverts it and outputs it. As can be seen from this configuration, a delay circuit is used, and such a delay circuit is usually a capacitor connected between the inverter and this output and ground or such a configuration. It consists of a number of subordinate connections.

As shown in FIG. 1, a delay circuit is essentially required when configuring an ATD circuit. Referring to FIG. 2 attached to the configuration of the delay circuit, a PMOS transistor Q1 and an NMOS transistor Q2 are described. And a capacitor 22 connected between the output terminal of the inverter 2 and the ground. The operation characteristics of the delay circuit include a resistance component and a capacitor 22 of the inverter 21. The signal a input to the inverter 21 is delayed and outputted by the RC time constant of?.

At this time, the important parameters for the signal delay of the delay circuit are the resistance component (R) and the capacitance component (C) as raised, the capacitance component can be fixed to any constant value during manufacture, while the resistance component has several dependent variables. Will be affected.

That is, the resistance component may be expressed as a function of the power supply (Vcc), the temperature (T), and the variables according to the wafer process as dependent variables, which means that the factor causing the output to appear later than the point where the input occurs is dependent on the dependent variable. It means that it is affected by the change of the variable.

This will be described in more detail with reference to FIG. 3.

As shown in FIG. 2, the delay circuit includes a inverter 21 having a CMOS configuration including a PMOS transistor Q1 and an NMOS transistor Q2, and a capacitor 22 connected between the output and the ground. When the input is at the low level or the ground level, the operation of the circuit is charged to the capacitor 22 by establishing the path of the current flow leading to the PMOS transistor Q1 and the capacitor 22 and the ground turned on as shown in FIG. 3 (a). Is charged. At this time, since the gate-to-source voltage Vgs of the PMOS transistor Q1 is the power supply voltage Vcc, and the mutual conductance of the PMOS transistor Q1 is proportional to the power supply, that is, the time that is charged in the capacitor 22, that is, the delay time. Appears in proportion to the power source.

On the other hand, when the input is at the high level or the power level, the circuit operation at this time discharges the charge that was charged in the capacitor to the ground by the turned-on NMOS transistor Q2 as shown in FIG. 3 (b). Also in this case, since the gate-source voltage Vgs of the turned-on transistor is the power supply voltage Vcc, the delay time is related to the power supply.

Therefore, it can be seen that the main deciding variable in the delay time is the voltage level of the power supply used. In recent years, a personal computer often uses a 3V power level lower than a 5V power supply to use the power more efficiently. It is becoming.

As described above, despite the fact that the delay time is related to the power source, there is a problem in that the variation of the delay time is large because the same circuit is used in any case regardless of the change of the power level.

Furthermore, in the system designed to use various power supply voltage levels, the above-described problems are greatly added. Therefore, a delay circuit capable of outputting an output signal with a constant delay time is required even if the power supply levels are differently applied. It is true.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to provide a delay circuit capable of delaying and outputting an input signal with a constant delay time regardless of a change in power level.

In addition, another object of the present invention is to provide a delay circuit that can additionally adjust and set the width of the delay time in achieving the above object.

Another object of the present invention is to provide an ATD circuit using a delay circuit in the SRAM ATD circuit that achieves the above-described object.

A feature of the present invention for achieving the above object is a delay circuit having at least one circuit composed of an inverter having a CMOS configuration and a capacitor connected in parallel between the output terminal and ground of the inverter, wherein the delay circuit is input to the delay circuit. A first reference voltage which is proportional as more drive powers are input based on when the drive power source reaches a predetermined value, but generates an increase rate of which increases at a relatively small rate relative to the increase rate of the drive power source; Generating means, second reference voltage generating means for generating a constant voltage even if more driving powers are input based on when the driving power reaches a predetermined value, power applied to the MOS element constituting the inverter, and the MOS Interposed between devices and receiving the driving power and inputting the driving power to the delay circuit, wherein the first reference voltage generating means And a voltage drop means for dropping the driving power to provide the charging voltage of the capacitor, and the ground connected to the MOS device constituting the inverter and the second MOS device. And a discharge rate maintaining means for keeping the resistance component of the discharge path of the capacitor constant by using the voltage signal generated by the reference voltage generating means as a control signal.

Another characteristic of the present invention for achieving the above object is proportional to the higher driving power is input based on when the input driving power reaches a predetermined value, but the increase rate is relatively higher than the increase rate of the driving power. A first reference voltage generating circuit for generating a voltage which increases at a very small rate; and a second reference voltage generating circuit for generating a constant voltage even if more driving powers are input based on when the driving power reaches a predetermined value. And a delay controller comprising first and second switching means switched by receiving reference voltages generated by the first and second reference voltage generating circuits, and a capacitor connected between the inverter of the CMOS configuration and the output of the inverter and ground. A delay circuit including at least one circuit configured, wherein the first switching means of the delay controller Is interposed between the power applied to the MOS device and the MOS device, and the second switching means of the delay controller is interposed between the ground connected to the MOS device constituting the inverter and the MOS device.

Another feature of the present invention for achieving the above object is the generation of the first and second reference voltage to generate a constant reference voltage even if more power is input based on when the applied power reaches a predetermined value And a delay circuit including at least one circuit comprising a circuit, a delay controller comprising a transmission gate switched by receiving the reference voltage, and a circuit comprising an inverter having a CMOS configuration and a capacitor connected between the output of the inverter and the ground and the delay controller. The transmission gate of the controller is connected between the inverter and the capacitor constituting the delay circuit.

According to another aspect of the present invention, an NOR gate receiving an address and a chip enable (CEX) signal and an output signal of the NOR gate are provided in an address transition detection (ATD) circuit of a static RAM (SRAM). A delay circuit for delaying the signal, an inverter for inverting the output of the delay circuit and the output of the NOR gate and performing an exclusive-or logic operation, and an inverter for inverting the output of the XOR gate; And a delay controller comprising first and fourth reference voltage generator circuits for supplying the first and second reference voltage supply means, and the XOR gate output switches the first reference voltage generator circuit and inverts the XOR gate output. The output is connected to switch the second reference voltage generating circuit.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a diagram illustrating a detailed circuit configuration of a delay circuit according to the present invention. Referring to FIG. 5, the operation of an embodiment according to the present invention configured as shown in FIG. 4 is as follows.

First, the operation of the first reference voltage generator 91 will be described with reference to FIG. 5A. Since the ground potential is applied to the gate terminals of the first to third PMOS transistors Q7 to Q9, the turn-on state is always turned on. Accordingly, when the power supply voltage Vcc is 0V, the output voltage V1 using the first reference voltage is also maintained at 0V. At this time, when the power supply voltage Vcc gradually rises, the state of the output voltage may be displayed as a section from P1 to P3 according to the level of the rising voltage.

Referring to the section P1, the power supply voltage Vcc, which is currently increased by the first PMOS transistor Q7 in the turn-on state, is applied to the first node NA, but is greater than the breakdown voltage of the first PMOS transistor Q7. Since the state before the increase, the actual voltage applied to the first node NA is in a state in which the voltage is lowered than the voltage level of the power supply voltage Vcc. Thereafter, the voltage applied to the first node NA is dropped again by the second and third PMOS transistors Q8 and Q9 to be output to the output voltage V1. In this period, the increase in the power supply voltage results in the first NMOS. The period in which the transistor Q11 cannot be turned on is a short period that can be almost ignored.

Thereafter, when the power supply voltage Vcc increases and the first NMOS transistor Q11 is turned on, the current driving force of the first NMOS transistor Q11 is greater than that of the third PMOS transistor Q9, so the output voltage V1 is a ground potential. Will remain low. At this time, since the voltage applied to the first node NA is maintained within the range of the breakdown voltage of the fourth PMOS transistor Q10, the fourth PMOS transistor Q10 is maintained in the turned off state. This state is the P2 section.

Thereafter, when the power supply voltage rises again and the voltage applied to the first node NA becomes greater than the breakdown voltage of the fourth PMOS transistor Q10, the output voltage V1 is caused by the fourth PMOS transistor Q10. This rises slowly. This interval is indicated as P3.

Looking at the operation of the second reference voltage generation circuit 92 corresponding to the operation of the first reference voltage generation circuit 91 operating as described above with reference to FIG. 5 (b), the power supply voltage Vcc is 0V. In case of, the output voltage V2 used as the second reference voltage is also maintained at 0V. Since the fifth PMOS transistor Q12 maintains the turn-on state, the power supply voltage Vcc that increases as the power supply voltage Vcc gradually increases is represented as the output voltage V2. At this time, since the second to fourth NMOS transistors Q13 to Q15 are turned off, the output voltage V2 maintains the voltage level of the power supply voltage Vcc in its present state. This interval is P4.

Thereafter, when the voltage level of the power supply voltage Vcc is increased, the second to fourth NMOS transistors Q13 to Q15 are gradually turned on so that a voltage signal having a level lower than the power supply voltage Vcc is represented as the output voltage V2. . At this time, the output voltage V2 gradually increases since the fifth PMOS transistor Q12 has a larger current driving ratio than the second through fourth NMOS transistors Q13 through Q15. However, the fifth NMOS transistor Q16 remains turned off because the voltage difference between the third node NC and ground is insufficient to turn on the fifth NMOS transistor Q16. The section showing such a state is the P5 section.

Thereafter, when the power supply voltage VCC increases and the voltage applied to the third node NC turns on the fifth NMOS transistor Q16, the magnitude of the output voltage V2 is substantially the fifth PMOS transistor Q12 and the fifth NMOS. According to the partial pressure of the transistor Q16, if the current driving ratio, that is, the size of the fifth NMOS transistor Q16 is appropriately adjusted and designed, the power supply voltage Vcc is used as the second reference voltage even if a further voltage rise occurs. It can be configured as a voltage source that the output voltage (V2) is no longer increased. The section showing such a state is the P6 section.

The voltage output from the first and second reference voltage generators 91 and 92 operating in this manner is used as a signal for controlling the turn on / off of the first and second switching means 62 and 63.

At this time, the characteristics of the first and second switching means 62 and 63 are used as a path on / off means for inputting the power supply voltage Vcc to the driving power supply by the delay circuit 61, and thus the voltage charging path of the delay circuit. It is used as a variable resistance element on the discharge path.

In other words, the characteristics of the MOS transistor are briefly described. First, the depth of a channel maintained in the on state of the PMOS transistor is inversely proportional to the magnitude of the voltage input to the gate terminal, and the depth of the channel maintained in the on state of the NMOS transistor is increased. As the proportion of the voltage input to the gate terminal is proportional, the resistance component of the MOS transistor also varies according to the depth of the channel that varies according to the magnitude of the voltage applied to the gate terminal.

Accordingly, the reference voltage V1 generated by the first reference voltage generating circuit 91 is varied as shown in FIG. 5A attached by the power supply voltage Vcc, which is the first reference voltage. The PMOS transistor Q3 of the switching means 62 which receives (V1) at the gate terminal maintains the degree of voltage applied to the PMOS transistor Q4 of the delay circuit 61 at a predetermined level.

Accordingly, the first reference voltage V1 is the PMOS transistor Q3 which is the first switching means 62 connected between the source and the power supply terminal of the PMOS transistor Q4 of the CMOS circuit constituting the inverter included in the delay circuit 61. The first switching means is turned on by the generated reference voltage and the second reference voltage V2 is connected between the drain and the ground of the NMOS transistor Q5 of the CMOS circuit. Is applied to the gate of the NMOS transistor Q6 so that the second switching means is turned on by the generated reference voltage V2, so that the input c applied to the inverter with the first and second switching means turned on is At the low level, the capacitor is charged with charge according to the operation principle of FIG. 3 (a), and when the input is at the high level, the charge of the capacitor is discharged according to the operation principle of FIG. 3 (b).

Note that the reference voltage circuit unit 9 and the switching means 62 and 63 according to the present invention operating as described above constitute a delay controller for the delay circuit 61.

The delay controller maintains a constant delay time for the multilevel power supplied to the delay circuit 61 to delay and output the input signal, and at the same time adjust the reference voltage, that is, the reference voltage circuit of the delay controller. By adjusting the size of the MOS transistor, the Vcc dependence of the delay time can be arbitrarily adjusted.

Next, a second embodiment according to the present invention will be described next.

As shown in FIG. 6, the circuit diagram according to the second embodiment differs from the first embodiment in that the transfer gate 64, which is operated by receiving a reference voltage, has a PMOS Q17 configured in a delay circuit. It is interposed between the inverter of the NMOS Q18 and the capacitor C3, and the basic configuration of the reference voltage generating circuit 9 and the delay circuit 61 is the same as in the first embodiment.

The output of the reference voltage generating circuit which generates a constant reference voltage with respect to the level of power is applied to the control terminal of the transfer gate and is enabled at that level, so that the output of the inverter passes through the transfer gate to the capacitor or is charged. The charge passes through the transfer gate and is discharged through the NMOS transistor Q18 of the inverter.

As described above, the delay circuit of the present invention can be suitably applied to form an ATD circuit of an SRAM.

FIG. 7 is a block diagram of an ATD circuit of an SRAM constructed by employing the delay circuit of the present invention, and FIG. 7 is a circuit diagram embodied using circuit elements based on the configuration of FIG.

As shown in FIG. 7, the delay circuit is operated by receiving the output of the reference voltage generating circuit 9 called V1 and V2, and the reference voltage generating circuit 9 is operated based on the output of the ATD circuit. In this circuit configuration, the clock pulse signals φ and ^* φ output from the ATD are fed back to the reference voltage generating circuit so that the reference voltage is generated only during the period in which the pulse is generated, and in other periods, the first reference voltage is Vcc and The second reference voltage is set to the ground level.

An example of a specific circuit of the present invention which realizes this is shown in FIG. 8, and waveform diagrams illustrating the operation of this circuit are shown in FIGS. 9 shows an operating state at 5V, and FIG. 1 shows an operating state at 3V.

In FIG. 8, the ATD circuit according to the present invention includes a NOR gate 5 receiving an address ADDI and a chip enable signal CEX, a delay unit 6 delaying an output signal of the NOR gate 5; An XOR gate 7 that receives an output of the delay unit 6 and an output of the NOR gate 5 and performs an exclusive-or logic operation, an inverter 8 that inverts the XOR gate output, and the delay circuit And a reference voltage generating circuit 9 for supplying a reference voltage. The XOR gate output is ^* φ, which is applied to the gate of the switching PMOS transistor Q48 of the first reference voltage generator circuit 91 and the output φ of the inverter 8 which inverts the XOR gate output is the second reference voltage generator circuit 92. Is connected to the gate of the switching NMOS transistor Q44.

Then, at the point where the address signal ADDI changes as shown in the waveform diagram A of FIG. 9 showing the operating state at 5V, the clock pulse which is the output of the ATD appears as B of FIG. Are operated to output the voltages V1 and V2 as shown in C and D of FIG. Similarly, the waveform of FIG. 10 representing the operating state at 3V also shows the above state, and only the magnitude of the signal is shown different from FIG.

As such, by feeding back the ATD output, the reference voltage generation circuit is prevented from operating at all times, thereby minimizing DC power consumption. In addition, instead of the ATD output, it is also possible to apply CEX and its inverted signal to the reference voltage generation circuit to operate.

The delay circuit according to the present invention is applied not only to the above-described ATD circuit but also to a WTD (Trite Transition Detection), a Data Transition Detection (DTD), or an equivalent circuit configuration.

Claims (10)

A delay circuit having at least one circuit comprising an inverter having a CMOS configuration and a capacitor connected in parallel between an output terminal of the inverter and a ground, the delay circuit comprising: a driving power input to the delay circuit when a predetermined value is reached; First reference voltage generating means for generating a voltage which is proportional as the above-described driving power is input but whose increase rate is increased at a relatively small rate compared to the increase rate of the driving power; Second reference voltage generating means for generating a constant voltage even when more than one driving power is input based on when the driving power reaches a predetermined value; The driving power is interposed between the power applied to the MOS device constituting the inverter and the MOS device, and receives the driving power and inputs the driving power to the delay circuit, using the voltage signal generated by the first reference voltage generating means as a control signal. A voltage drop means for dropping the voltage to provide the impact voltage of the capacitor; A discharge rate interposed between the ground connected to the MOS device constituting the inverter and the MOS device, the voltage signal generated by the second reference voltage generating means as a control signal to maintain a constant resistance component of the discharge path of the capacitor; A delay circuit comprising a holding means. The first driving voltage state of claim 1, wherein the first reference voltage generating means connects a predetermined number of PMOS transistors in series to increase the size of the transistor resistance to detect whether an increase state of the driving voltage increases beyond a certain size. A detector; A voltage signal generator configured to adjust the magnitude of the voltage applied to the output terminal by performing an on / off operation according to a state of a voltage branched at an arbitrary connection point of the transistor included in the driving voltage state detector; And suppressing the magnitude of the voltage signal output through the voltage signal generator by conducting a current through the first driving voltage state detector to ground when the increase state of the driving voltage increases by more than a predetermined magnitude. A delay circuit comprising a negative. 2. The apparatus of claim 1, wherein the second reference voltage generating means comprises: a voltage drop unit for decreasing and increasing the driving voltage by a predetermined magnitude; A second driving voltage state detection unit which connects a predetermined number of NMOS transistors in series to increase the magnitude of the transistor resistance to detect whether the voltage output from the voltage drop unit is increased by more than a predetermined size; The second driving voltage state detector may be increased when a current driving rate increases according to a state of a voltage branched at an arbitrary connection point of the transistor included in the driving voltage state detection unit so that the increase state of the driving voltage increases by more than a certain amount. And a second signal magnitude suppressing portion for suppressing the magnitude of the voltage signal outputted through the voltage dropping portion by conducting a current passing through to ground. The driving voltage applied to the delay circuit of claim 1, wherein the voltage drop means uses a PMOS transistor whose current drive rate is controlled according to a voltage signal generated by the first reference signal generating means. A delay circuit characterized by suppressing the increase. The discharge rate of the charge charged in the capacitor in the delay circuit by using the NMOS transistor whose current driving rate is controlled in accordance with the voltage signal generated by the second reference signal generating means. Delay circuit, characterized in that to adjust. A first criterion for generating a voltage that is proportional to the higher driving power input based on when the driving power input reaches a predetermined value, but increases in proportion to a relatively small rate compared to the increasing power of the driving power. A voltage generating circuit; A second reference voltage generating circuit which generates a constant voltage even when more driving powers are input based on when the driving power reaches a predetermined value; A delay controller comprising first and second switching means switched by receiving reference voltages generated by the first and second reference voltage generation circuits; And a delay circuit including at least one circuit comprising a capacitor configured to be connected between the inverter of the CMOS configuration and the output of the inverter and a ground, wherein the first switching means for the delay control is a power source applied to the MOS device constituting the inverter; And a second switching means of the delay controller is interposed between the MOS devices and interposed between the ground and the MOS devices connected to the MOS devices constituting the inverter. First and second reference voltage generating circuits that generate a reference voltage even when more than one power source is input based on when an applied power source reaches a predetermined value, and a delay comprising a transmission gate that is supplied with the reference voltage and switched. And a delay circuit including at least one circuit comprising a controller and a capacitor configured to be connected between the inverter of the CMOS configuration and the output of the inverter and the ground, and the transmission gate of the delay controller is connected between the inverter and the capacitor constituting the delay circuit. Delay circuit, characterized in that. An address transition detection (ATD) circuit of a static RAM (SRAM), comprising: a NOR gate that receives an address and a chip enable (CEX) signal, a delay circuit that delays an output signal of the NOR gate, an output of the delay circuit, and the NOR gate An XOR gate that performs an exclusive-or logic operation upon receiving an output of an output, an inverter that inverts an XOR gate output, and a first and second reference voltages connected to the delay circuit to supply a reference voltage to control a delay time. A delay controller comprising a circuit and first and second switching means, the output of the XOR gate switching the first reference voltage generating circuit and the output of the inverter inverting the output of the XOR gate switching the second reference voltage generating circuit. ATD circuit of the SRAM, characterized in that connected to. The MOS circuit of claim 8, wherein the delay circuit comprises at least one circuit comprising an inverter having a CMOS configuration and a capacitor connected between an output of the inverter and a ground, wherein the first switching means of the delay controller is a MOS configuring the inverter. And a second switching means of the delay controller is interposed between the power applied to the device and the MOS device, and between the ground connected to the MOS device constituting the inverter and the MOS device. 10. The apparatus of claim 8, wherein the delay circuit comprises at least one circuit composed of a capacitor connected between an inverter of a CMOS configuration and an output of the inverter and a ground, wherein the delay controller is configured when the applied power reaches a predetermined value. And a first and second reference voltage generator circuits which generate a reference voltage constantly even when more than one power source is input, and a transmission gate which is switched to receive the reference voltage. ATD circuit of the SRAM, characterized in that connected between the inverter and the capacitor constituting the circuit.