KR970003980B1 - Echo canceller circuit in plmn - Google Patents

Abstract

Echo canceller circuit has a plurality of digital signal processor(DSP) by using one-chip controller, thereby achieving a simplified circuit. The circuit includes: a control bus matching circuit(100)l; a controller(200) for performing a control function to remove an echo generated at 2line/4line hybrid of a public switched telephone network when receiving a voice of a PLMN subscriber; a memory(31) for storing a digital signal processing program; a DSP circuit(320) for removing the echo by filtering PCM audio data signal from the 2line/4line hybrid; and a PCM sub-highway matching circuit(400) which is connected between a time switch apparatus and the DSP circuit(320), and performs a transmitting/receiving of a PCM audio data signal of which echo is to be removed.

Description

Echo cancellation circuit in mobile telecommunication switching network

1 is a block diagram schematically showing the configuration of an echo cancellation circuit according to the present invention;

2 is a block diagram showing the detailed configuration of the DSP circuit 320 of FIG.

3 is a block diagram showing a detailed configuration of the PCM subhighway matching circuit 400 of FIG.

4 is a timing diagram of sync pulses provided to respective DSPs of FIG.

5 is a PCM channel allocation timing diagram of each DSP serial port of FIG.

* Description of the symbols for the main parts of the drawings *

100: control bus matching circuit 200: control unit

210: 1 chip controller 220: decoder and latch circuit

230: interrupt encoder 300: DSP unit

310: EPROM320: DSP circuit

321 to 32n: DSP0 to DSPn400: PCM subhighway matching circuit

410: counter circuit 420: decoder circuit

430: selection circuit 440: buffer

The present invention is directed to an echo canceler circuit for canceling echoes generated during interworking of a digital pulse length modulation network (PLMN) and a public switched telephone network (PSTN). More specifically, it relates to an echo cancellation circuit having a plurality of digital signal processors (DSPs) using a one-chip controller.

When the digital mobile telecommunication switching network (PLMN) and the public switched telephone network (PSTN) are interworked, when a voice transmission is made from a mobile subscriber (hereinafter, referred to as a "mobile communication subscriber") of the mobile telecommunication switching network, the voice of the mobile subscriber is transmitted through A public telephone network is transmitted to a fixed subscriber (hereinafter referred to as a 'telephone network subscriber') through a public telephone network through a public telephone network via a switching network to a fixed subscriber of a public telephone network (hereinafter referred to as a 'telephone subscriber'). Echo occurs due to impedance mismatch of the 2-wire / 4-wire hybrid in the network matching portion of the telephone network subscriber. These echoes are delayed by about 180ms round-trip due to voicecoding for the efficiency of the wireless channel in the PLMN, so it is necessary to eliminate the echoes because it makes the call uncomfortable. do.

It is an object of the present invention to make the circuit simple and economical in the implementation of an echo cancellation circuit which eliminates such echo.

The present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram showing the configuration of an echo cancellation circuit according to the present invention. Referring to FIG. 1, the echo cancellation circuit of the present invention includes a control bus matching circuit 100 for exchanging information with a control processor for controlling transmission and reception of a PCM voice data signal, and general control functions related to echo cancellation. And a DSP unit 300 for performing filtering on the PCM voice signal by downloading a predetermined digital signal processing program according to the instruction of the controller 200. In addition, a sub-highway matching circuit 400 is required for smoothly transmitting and receiving a PCM voice data signal between a time switching processor and a DSP. When the voice transmission is made from the mobile subscriber of the PLMN, that is, the mobile communication subscriber, the controller 200 executes a predetermined control program to perform general control related to the removal of echoes generated in the 2-wire / 4-wire hybrid of the PSTN. Decoder and latches that accept a controller 210 that performs a control function and an address of the controller 210 as input, select a required device, and latch control data necessary for the controller 210 to control a plurality of DSPs. A circuit 220 and an interrupt encoder 230 for allowing the controller 210 to manage interrupts output from the plurality of DSPs, respectively. The DSP unit 300 performs an EPROM 310 for embedding a digital signal processor program (DSP) and a DSP circuit 320 for substantially performing echo cancellation by executing a DSP program downloaded from the EPROM 310. It is composed of

2 shows a detailed configuration of the DSP circuit 320 according to the present invention. Referring to FIG. 2, the DSP circuit 320 according to the present invention includes a plurality of digital signal processors (DSPs) 321 to 32n serving as a digital adaptive filter for echo cancellation. In FIG. 2, each of the plurality of DSPs 321 to 32n is connected to the decoder and latch circuit 220, the EPROM 310, and the PCM subhighway matching circuit 400, respectively. The decoder and latch circuit 220 is connected to the plurality of DSPs and, in response to an address of the controller 210 being input, selects one of the plurality of DSPs and controls the plurality of DSPs. To latch the control data provided from the controller 210 to deliver to the selected one DSP or latch the data provided from the selected one DSP. The plurality of DSPs 321 to 32n communicate with the controller 210 using common buses, and two pairs of serial transmission / reception of each of the DSPs 321 to 32n each have a PCM voice data signal necessary for echo cancellation. Send and receive using the port.

3 shows a detailed configuration of the PCM subhighway matching circuit 400 of the echo cancellation circuit according to the present invention. Referring to FIG. 3, the PCM subhighway matching circuit 400 includes a counter circuit 410 for generating a predetermined clock in response to a clock CLK and a synchronization pulse FS provided from a time switch device, and a counter circuit. A decoder circuit 420 for providing a synchronization clock suitable for each of the plurality of DSPs 321 to 32n in response to a clock provided from 410, and a plurality of decoders in response to a clock provided from the counter circuit 410. When the DSPs 321 to 32n transmit the echo canceled PCM voice data to the time switch device, a plurality of DSPs 321 to 32n simultaneously transmit data to the serial transmission port, thereby preventing a data collision. To open the serial transmission path of the corresponding DSP among the plurality of DSPs 321 to 32n by using the signal received from the counter circuit 410 so that the data transfer of the other DSP is prevented due to the generated DSP. tile Receives a selection circuit 430 that closes, a reference input signal DI required for echo cancellation received from the time switch device, and a signal DR mixed back via a 2-wire / 4-wire hybrid of a fixed subscriber; The buffer 440 for sending to the DSP of the.

In the echo cancellation circuit according to the present invention, in order to embed the DSP program necessary for the operation and control of the DSP, control of the one-chip controller 210 for controlling the echo cancellation circuit without allocating a program ROM or data RAM for each DSP is performed. The plurality of DSPs 321 to 32n are commonly connected through the data bus and the address bus so that the plurality of DSPs download the program from the EPROM 310 to the internal RAM.

Here, for the sake of simplicity and convenience of explanation, a case where the DSP circuit 320 is composed of eight DSPs will be described in detail later.

Each of the eight DSPs receives the transmit / receive synchronization clock of the serial port allocated to it from the PCM subhighway matching circuit 400 which generates eight transmit / receive synchronization clocks having different timings, and uses the received clock as a synchronization signal. Four channels of PCM data are selectively received from the serial signal line and transmitted simultaneously.

4 is a timing diagram of the clock CLK and the sync pulse FS output from the time switch device and the sync pulses DFS0 to DFS7 of each DSP output from the PCM subhighway matching circuit 400 of FIG. . The clock CLK output from the time switch device is 2.048 MHz, and the sync pulse FS starts at the rising edge of the clock CLK and maintains a high level for one period of the clock CLK. It falls to " low " at the rising edge of the clock CLK, which has a period of 125 ms.

The synchronization pulse DFS0 provided to the first DSP0 321 is generated by the "OR" of the pulse generated after the synchronous pulse (FS) and 16 cycles of CLK after the generation of the synchronization pulse. This first pulse causes the DSP0 321 to be serialized. It is used as a signal to receive or transmit 16 bits (2 channels) of data, that is, channels 0 and 1, through a transmission / reception port. The second one of the synchronization pulses (DFS0) of the DSP0 321 occurs 16 clocks after the first synchronization pulse, which is also a signal that causes the DSP0 321 to receive or transmit 16 bits (two channels) of data. DSP0 321 is used to cover the first four of the 32 channels provided by the time switch device. The DSP1 sync pulse DFS1 provided to the DSP1 322 is the first sync clock generated 16 clocks after the second sync pulse of the DSP0 321 as shown in FIG. 4, and the DSP1 322 is like the DSP0 321. It accepts or transmits 16 bits (2 channels) of data as a synchronous clock signal, and transmits and receives two channels as signals for the second synchronous clock occurring 16 clocks after the first synchronous clock. Thus, the DSP1 322 transmits channel 4 of 32 channels. It is responsible for four channels from to channel 7. By applying the same method to the DSP7 328, the DSP7 328 receives or transmits information on four channels from channels 28 to 31. Synchronous pulse (FS) is connected to the interrupt terminal of each DSP. When the synchronization pulse (FS) comes in, each DSP generates an interrupt. At this time, each DSP recognizes 32 new channel frames, which is related to DSP internal counter and serial transmission / reception port. Clear the registers.

FIG. 5 is a timing diagram of the channel described above. Here, eight DSPs 321 to 328 show only DX, which is PCM voice data transmitted to a time switch device through a serial transmission port. The PCM voice data (DI, DR) received from the time switch device through the serial receiving port (~ 328) also has a channel timing diagram in the form of DX.

The operation of this example will now be described in detail with reference to FIGS. 1 to 5. Referring to FIG. 1, when the echo cancellation circuit is powered on or reset, the controller 210 is operated by a predetermined program embedded in an internal ROM (not shown). At this time, the controller 210 is initialized first. After the initialization of the controller 210 ends, the DSP0 321 starts to download under the control of the controller 210. In this case, only DSP0 321 can access the external EPROM 310 and the external bus and signal lines of the other DSPs 322-328 can be controlled by the controller 210 by the decoder and latch circuit 220. High impedance to prevent DSP0 321 from affecting downloading of DSP programs from EPROM 310 to internal memory of DSP0321. When the downloading of DSP0 321 is finished, it goes to the downloading of DSP1 322. In this case, only DSP1 322 can bring the DSP program built into EPROM 310 to its internal memory through the external bus and signal lines. The DSP0 321 and the other DSPs 323 to 328 have high impedance in the external bus and signal lines in the same manner as described above, and thus do not affect the downloading of the DSP1 322. In this way, up to the eighth DSP, DSP7 328, under the control of the controller 210, DSP programs from one EPROM 310 are respectively downloaded to the internal memory of the DSP.

In this way, the address bus and the data bus of the EPROM 310 are commonly connected to the eight DSPs 321 to 328 so that the eight DSPs 321 to 328 have access in common. The collision can be prevented.

In the communication between the controller 210 and any of the eight DSPs 321 to 328, the controller 210 decodes all the external buses and signal lines of the DSP except the DSP that communicates with the controller 210 as described above. And by making the high impedance state using the latch circuit 220 can communicate without data collision without using a separate bus arbitration circuit.

After the downloading of the eight DSPs 321 to 328 is completed, each DSP receives a signal from the controller 210 and each DSP performs an echo cancellation program to eliminate echoes. Each of the eight DSPs 321 to 328 receives 32 channels of PCM voice data from the time switch device through the PCM subhighway matching circuit 400, which is to be echo canceled. CLK and the sync pulse FS are received by the counter circuit 410 of the PCM subhighway matching circuit 400 and used to generate the input signal of the decoder circuit 420, resulting in two successive syncs as shown in FIG. DSP synchronous pulses DFS0 to DFS7 having pulses are provided to the eight DSPs 321 to 328, respectively.

Since the serial transmit / receive ports of each DSP are set in the burst mode, 16 bits (two channels) are received or transmitted in response to the DSP sync pulses DFS0 to DFS7, and thus the DSP sync pulses DFS0 to FIG. DFS7), each DSP is shown in FIG. 5, such that DSP0 321 is responsible for channels 0 to 3 among 32 channels, and DSP1 322 is responsible for channels 4 to 7, and four channels per DSP. Each of the eight DSPs 321 to 328 processes 32 channels.

Each DSP uses a PCM voice data (DI) signal transmitted from a mobile subscriber to a fixed subscriber using a serial receive port as a reference input signal to create a duplicate echo signal to generate the mobile subscriber's mobile station. By subtracting the duplicated echo signal from the signal DR from the fixed subscriber with echo, the echo canceled signal DX is transmitted to the time switch device and transmitted to the mobile subscriber.

At this time, of the three signals DI, DR, and DX, DI and DR are 32 channel PCM voice data signals received from the time switch device, and DX is a PCM voice data signal having 32 channels transmitted to the time switch device. .

As described above, through the PCM subhighway matching device 400, each DSP receives four channels to be echo canceled and the controller 210 echo cancels any channel among four channels to each DSP according to a command of the control processor. (Or stop echo cancellation), each DSP performs the echo cancellation (or echo cancellation) function for that channel among its four channels and, as described above, the PCM subhighway matching device. Four channels are transmitted to the time switch device 400.

As described in detail by way of example above, in the present invention, since each of the plurality of DSPs 321 to 32n from one EPROM 310 downloads the DSP program to its internal memory, There is no need to allocate a program ROM or data RAM, but an address bus and a data bus in which the one-chip controller 210 and the decoder and latch circuit 220 are commonly connected between the EPROM 310 and the plurality of DSPs 321 to 328. By arbitration, data collisions can be prevented without a separate bus arbitration circuit.

In addition, by allowing the reception and transmission of four channels out of 32 channels of PCM voice data through the serial transmit / receive port of each DSP without heavy DSP load, it is possible to give four channels of echo cancellation function per DSP. Application of the invention makes it possible to construct a simple and economical echo cancellation circuit.

Claims (3)

A circuit for eliminating echoes generated during interworking between a digital mobile telecommunication switching network (PLMN) and a public telecommunication network (PSTN); A control bus matching circuit 100 for exchanging information with a control processor for controlling transmission and reception of PCM voice data signals; When the voice transmission from the mobile subscriber of the PLMN is made through the control bus matching circuit 100, a control function for removing echoes generated in the 2-wire / 4-wire hybrid of the public telephone network by executing a predetermined program. A control unit 200 performing the operation; The memory 310 storing the digital signal processing program and the digital signal processing program after downloading the digital signal processing program from the memory 310 in response to an instruction of the controller 200, and then executing the digital signal processing program to perform the digital telephone processing network. A DSP unit (300) comprising DSP circuitry (320) for canceling echoes by performing filtering on mixed PCM speech data signals from the 2-wire and 4-wire hybrids of the? A PCM subhighway matching circuit 400 connected between the time switch device and the DSP circuit 320 for transmitting and receiving the echo canceled PCM voice data signal and the PCM voice data signal to be echo canceled therebetween. Echo cancellation circuit of a mobile communication switching network. The method of claim 1; The DSP circuit 320 includes a plurality of digital signal processors (DSPs) 321 to 32n respectively connected between the controller 200 and the PCM subhighway matching circuit 400; The controller 200 is connected to the controller 210 performing all control functions related to echo cancellation, the plurality of DSPs, and in response to an address of the controller 210 being input, the plurality of DSPs. In addition to selecting one, the control data provided from the controller 210 is latched and transferred to the selected one DSP or the data provided from the selected one DSP is latched to control the plurality of DSPs. A mobile communication switching network comprising a decoder and a latch circuit 220 for transmitting to the controller 210 and an interrupt encoder 230 for transmitting interrupts respectively output from the plurality of DSPs to the controller 210. Echo cancellation circuit in. The method of claim 1 or 2; The PCM subhighway matching circuit 400 includes a counter circuit 410 for generating a predetermined clock in response to a clock CLK and a synchronization pulse FS provided from the time switch device; A decoder circuit 420 for providing a synchronous clock to each of the plurality of DSPs 321 to 32n in response to a clock provided from the counter circuit 410; In response to the predetermined clock provided from the counter circuit 410, when the plurality of DSPs 321 to 32n transfer the echo canceled PCM voice data signal to the time switch device, the plurality of DSPs 321 to 32 n. The plurality of signals may be transmitted by using the signal received from the counter circuit 410 to prevent data conflicts that may occur when 32n) simultaneously transmits data to the serial transmission port, and to prevent data transmission of another DSP due to an errored DSP. A selection circuit 430 for opening the serial transmission path of the corresponding DSP among the DSPs 321 to 32n of the DSP while closing the serial transmission path of the other DSP; A buffer 440 for receiving a signal (DR) mixed with a reference input signal (DI) required for echo cancellation received from the time switch device and a return signal through a two-wire / four-wire hybrid of a fixed subscriber and transmitting it to each DSP. Echo cancellation circuit in a mobile communication switching network comprising a).