KR100198790B1 - Echo canceller - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an echo canceller for canceling echoes in a communication network. In particular, an echo filter (LADF) having a large number of taps and an adaptive filter having a small number of taps can be used to perform echo cancellation for multiple channels in one DSP. Disclosed is an echo canceller that can reduce the amount of computation even for impulse response with long delay using SADF).

Description

Echo canceller

The present invention relates to an echo canceller entering a digital mobile switching center. Echoes generated during the interworking of digital mobile telecommunication exchanges with existing public switched telephone networks (PSTNs) should be removed. This echo is caused by impedance mismatch due to a two-wire / four-wire hybrid circuit on the side of the public telephone network when the voice of the mobile subscriber is transmitted to the fixed subscriber through the public telephone network. Since voice coding is performed in the mobile communication exchange, there is a delay of about 90ms in the one-way, and the echo coming back to the mobile subscriber is accompanied by a delay of about 200ms including the pure channel delay, which makes the call uncomfortable. In general, in the echo path impulse response of a telephone network, the pure delay portion is composed of the diffuse reflection portion, and the size of the diffuse reflection portion does not exceed 32 taps (4 ms).

In the present invention, when the echo canceller is configured to remove the echo, an adaptive filter (LADF) having a large number of taps and a relatively large tap number are used for the non-recursive (FIR) adaptive filter for estimating the impulse response of the echo path. By using a small filter (SADF) to reduce the amount of calculation, it is possible to configure the economical echo cancellation device by allowing echo cancellation for multiple channels in one digital signal processing processor (DSP). Echo cancellation device according to the present invention is installed in conjunction with the time switch device for receiving a relay line connected to the digital mobile telecommunication switching network and the existing public telephone network, when transmitting the PCM voice data output from the digital mobile telecommunication switch to the existing public telephone network, echo The same data is also received by the rejection device and inputted to the adaptive digital filter in the echo canceller so that the signal obtained by estimating the impulse response to the delay and the echo of the path through the 2-wire or 4-wire hybrid of the public telephone network is airborne. It is to eliminate echoes coming back from the public telephone network by subtracting from the data coming from the telephone network. In this case, the impulse response of the domestic echo path appears for about 30ms, and a non-circular (FIR) adaptive filter with 256 or more taps should be used. Ineffective. The present invention relates to an effective echo canceller in order to be able to perform echo cancellation for multiple channels in one DSP in the configuration of an echo canceller for canceling the echo. By using a filter (SADF) with a relatively small number of taps and controlling it, the amount of calculation can be reduced even in a long delay impulse response.

1 is a block diagram illustrating the principle of an echo canceller according to the present invention;

2 is a block diagram of an echo cancellation circuit for applying the present invention.

3 is a detailed configuration of the echo canceller according to the present invention.

* Explanation of symbols for main parts of the drawings

100,400: delay due to voice coding and decoding

200: echo canceller 220: dual port RAM

230: control circuit 240: RS-232C matching circuit

250: booting EPROM 260: subhighway matching block

270 to 285: DSP 0 to DSP 15

300: hybrid circuit for 2-wire and 4-wire conversion 510: data delay circuit

520: small tap adaptive filter (SADF) 530: large tap adaptive filter (LADF)

540: multiplexer (MUX) 550: monitoring and control circuit

560: subtractor 570: nonlinear level processor

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

FIG. 1 is a block diagram illustrating the principle of an echo canceller according to the present invention and is a diagram of echo cancellation when a mobile communication network and an existing circuit-switching network connect. The voice data of the mobile subscriber A arrives at the echo canceller 200 in the PCM form through the process of coding and decoding the voice source according to the availability of the radio channel. In the processing of the voice data, a delay 100 of about 80 ms is generated. In this case, when echo cancellation is not performed in the echo canceller 200, the voice of the mobile subscriber A is partially echoed due to impedance mismatch in the hybrid circuit 300 of the public line telephone network, and the same delay in the reverse direction (400). After A), subscriber A hears his voice in reverberation and interferes with the call. In order to remove the echo as described above, the echo canceller 200 receives PCM-type speech data destined for the hybrid circuit 300 of the public telephone network as a reference signal, estimates a duplicate signal of the echo signal in the adaptive filter, and hybridizes the signal through the actual C. The echo is eliminated by subtracting from the signal passing through D through 300. In this case, subscriber B's voice is not damaged and subscriber A hears.

2 is a block diagram of an echo cancellation circuit for applying the present invention, which can be divided into five blocks according to a functional type of each circuit. The TD-bus (Telephony Device-bus) matching circuit 210 and the dual port RAM are shown in FIG. TD-bus matching block consisting of 220, control circuit 230 consisting of a 1-chip controller and peripheral circuits, control block including RS-232C matching 240, 16 DSPs (270 to 285), booting DSP block composed of EPROM 430, and sub highway matching block 260 to be matched with the time switch device.

The main function of the TD-bus matching block, consisting of the TD-bus (Telephony Device-bus) matching circuit 210 and the dual port RAM 220, is a serial mode / mode from a Time Switch Processor (TSP). It receives ADDR information, converts it into parallel form, analyzes it, generates an RDY signal, receives a control command from the TSP, and transmits status information to the TSP.

Looking at the components of the TD-bus (Telephony Device-bus) matching circuit 210, it is convenient to use the differential level signals and data received from the TSP when sending and receiving data to and from the TSP. In contrast, the RS-485 receiver for the TD bus converts to the TTL level, the RS-485 driver for the TD bus converts the signals and data of the TTL level to the differential level and transmits them to the TSP. TD-bus clock monitoring circuit to check, MODE / ADDR serial / parallel conversion circuit converting serial MODE / ADDR signal received from TSP into parallel form, and MODE / ADDR signal converted in parallel Paralleling the MODE / ADDR decoder that generates the signal, the RDY generation circuit that generates the RDY signal that informs the TSP that it is ready to send and receive data by inputting the ADDR signal of the MODE / ADDR decoder, and the serial data from the TSP. Turns into form And a dual port RAM control circuit for generating a signal for storing the data in the dual port RAM 220 and a signal for sending the data stored in the dual port RAM 220 to the TSP. Data parallel / serial conversion circuit converts parallel data into serial form to extract data stored in 220) and transmits to TSP, and dual port RAM 220 serving as a buffer to facilitate communication with TSP. do.

The configuration of the control circuit 230 includes a latch circuit composed of a one-chip controller responsible for control, a plurality of latches and peripheral circuits necessary for the one-chip controller to control 16 DSPs, and an address of the one-chip controller as an input. And a decoder for enabling the latch in the circuit and a reset circuit for resetting the entire circuit. The control circuit 230 is responsible for controlling the DSP and the peripheral circuit according to the control information received from the TSP to perform the echo cancellation function or to stop the echo cancellation function being performed, and to report the result to the TSP. do. The one-chip controller operates by the firmware by storing firmware in ROM and RAM embedded in the one-chip controller. By using a latch that acts as a buffer between the one-chip controller and the DSP, it overcomes the difference in data size and speed between the one-chip controller and the DSP, and also solves the bus arbitration function required for one-to-n communication. Communication between DSPs is smooth.

The subhighway matching block 260 prevents data collisions that may occur when multiple DSPs perform echo cancellation and transmit the processed data to the time switch device through the serial port of the DSP. It does not affect the data transmission using the serial port of the DSP. The sub-highway matching block 260 is a sub-highway (SHW) RS-485 receiver for converting the received sub-highway clock from the differential level to the TTL level received from the outside, and PCM voice data reversely removed RS-485 driver for subhighway (SHW) that converts from TTL level to differential level and transmits to time switch device, and subhighway (SHW) clock supervisory circuit that monitors the status of subhighway clock received through RS-485 receiver. The multiplexer uses the multiplexer to adjust the echo canceled PCM audio data from 16 DSPs to the time switch device in a timely manner so as not to cause a collision, and the subhighway clock received through the RS-485 receiver as input. It consists of a counter that provides the clock needed to operate.

Referring to the function and operation of the echo cancellation circuit to which the present invention is applied by the above-described configuration, it is initialized at power-on or reset, wherein 16 DSPs 270-285 are controlled under the control of the control circuit 230. Programs that perform echo cancellation functions from the boot EPROM 250 to the DSP 270 to 285 internal RAM are sequentially downloaded. If necessary, the current status may be displayed on the monitor through the RS-232C matching circuit 240 to check the status. When the voice PCM data of the mobile subscriber is transmitted to the relay line via a time switch accommodating the relay line, the same data is also input through two 32-channel PCM subhighways (SHWDI) to the echo cancellation circuit. One subhighway stores four channels in each DSP 270 to 277 for echo cancellation through the serial ports of the first eight DSPs 270 to 277. The other subhighway (SHWDI) stores four channels in each DSP 278 to 285 for echo cancellation through the serial ports of the remaining eight DSPs 278 to 285. Using the subhighway (SHWDI) as a reference input signal, the impulse response of the returning signal returned through the two-wire / four-wire hybrid circuit of the public telephone network is estimated to obtain an approximate echo signal, which is sent to the subscribers of the public telephone network as a mobile subscriber. Two 32-channel PCM subhighways (SHWDX) are transmitted to the time switch device by subtracting this approximated copy direction signal from the corresponding channel among the two 32-channel PCM subhighways (SHWDR). Since the time switch device sends this to the mobile subscriber, the mobile subscriber can talk with his echo removed.

The subhighway input and output to the echo cancellation circuit always passes through the time switch device. In performing the echo cancellation function, an allocation or other control command of the channel to be echo canceled is received from the TSP through the TD bus matching circuit 210, and the result or state of the channel is also transmitted to the TD bus matching circuit 210. Report to the TSP.

In the echo cancellation circuit as described above, 16 DSPs 270-285 sequentially perform a program for performing echo cancellation function from one boot EPROM 250 to the internal RAMs of DSPs 270 to 285 under the control of the control circuit 230. Downloaded by The echo cancellation program in the boot EPROM has the function of performing echo cancellation for several channels, and an adaptive filter having hundreds of taps is required for echo cancellation for one channel. In this case, a significant amount of computation is required, and for real-time configuration, the amount of computation must be reduced so that more channels can be processed in one DSP.

According to the present invention, the adaptive filter (LADF) 530 having a large tap and the adaptive filter (SADF) 510 having a small number of taps that can model the diffuse reflection part in the impulse response of the echo path, the monitoring and control circuit 550 and the digital data It is composed of a data delay circuit 510, a multiplexer 540, an adder and subtractor 560, which can delay by a set value.

3 is a block diagram of an echo canceller according to the present invention, and an adaptive filter (LADF: 530) having a large tap and an adaptive filter (SADF: 510) having a small number of taps that can be modeled in a diffuse reflection part in an impulse response of an echo path. And a data delay circuit 510 for delaying the monitoring and control circuit 550 and the digital data by a set value, a multiplexer 540, an adder and subtractor 560, and a nonlinear level processor 570.

At the initial convergence time of the echo canceller, the adaptive filter LADF 530 receives the reference input x (k) and receives the residual echo signal e (k), which is the output of the adder and subtractor 560, to continue the adaptive filtering to model the echo path. Perform.

The monitoring and control circuit 550 receives the residual echo signal e (k) and the echo input y (k) and calculates a power ratio using a low pass filter. When the power ratio reaches the preset target value, the monitoring and control circuit 550 determines that the initial convergence of the LADF 530 is finished, and sets the delay value of the data delay circuit 510 by receiving the number of delay taps from the LADF 530. do. While the data delay circuit 510 receives the reference input x (k) and delays it by the set delay value, the monitoring and control circuit 550 controls to transmit the tap coefficient of the diffuse reflection portion to the LADF 530 and the RK SADF 520. . When the SADF 520 normally starts to perform adaptive filtering, the monitoring and control circuit 550 controls the multiplexer (MUX) 540 to switch the output of the SADF 520 to be delivered to the adder and subtractor 540. do. When the SADF 520 operates through the above process, a normal convergence state is achieved.

In the normal converged state, the monitoring and control circuit 550 receives the reference input x (k) and the echo input y (k) and continuously tracks the power ratio to monitor the dual call state. When the double call state is established, the SADF 520 is controlled to prevent the coefficient update from being performed for a predetermined period (75 ms).

The monitoring and control circuit 550 also controls the nonlinear processing level of the nonlinear level processor in accordance with the power state of the echo input y (k). Adaptation of 256 taps after convergence in case of performing echo cancellation with the echo canceller configuration method of the present invention using the fact that the reflected part of the impulse response of the telephone network is relatively smaller than the pure delay part Instead of a filter, an adaptive filter with 32 taps of adaptive filtering is possible, which reduces the computation to almost 1/8 of the coefficient update. Using the above-mentioned echo canceller, it is possible to cancel the echo of several channels in one DSP, thereby enabling economical echo canceller configuration.

As described above, according to the present invention, since the echo canceller uses an adaptive filter (LADF) having a large number of taps and an adaptive filter (SADF) having a small number of taps, it is possible to reduce the calculation amount even for an impulse response having a long delay time. It is economical to be able to perform echo cancellation on multiple channels at.

Claims (5)

In the adaptive filter with the large tap and the impulse response of the echo path, the adaptive filter with the small number of taps that can model the non-reflective part, the supervision to calculate the power ratio using the low pass filter with the residual echo signal and the echo input, and A data delay circuit capable of delaying the control circuit and the digital data by a set value, a multiplexer for switching the output of the adaptive filter having a small number of taps, and an adaptive filter having a small number of taps according to the switching operation of the multiplexer And an non-linear level processor configured to process the data processed by the adder and subtractor according to the output signal of the monitoring and control circuit. 2. The echo canceller of claim 1, wherein the adaptive tap filter with a large number of taps is configured to receive a residual echo signal that is a reference input and an output of an adder / subtractor to model the echo path. The echo canceller of claim 1, wherein the monitoring and control circuit is configured to receive a residual echo signal and an echo input and determine an initial convergence by calculating a power ratio using a low pass filter. The method of claim 1, wherein the multiplexer receives a delay tap number from an adaptive filter having a large number of taps after the supervisory and control circuit finishes initial convergence, and sets a delay value of the data delay circuit. The adaptive filter with the number of taps is controlled to pass the tap coefficient of the diffuse reflection part, and when the adaptive filter with the small number of taps starts to perform the adaptive filtering normally, the output of the adaptive filter with the small number of taps is controlled by the multiplexer. Echo canceller, characterized in that switching to be delivered to the adder and subtractor. 2. The echo canceller of claim 1, wherein the monitoring and control circuitry is configured to control the nonlinear processing level of the nonlinear level processor in accordance with the power state of the echo input.