KR0152716B1 - Echo canceller in telephone network - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an echo canceller in a digital mobile communication switch. In particular, a parallel mode / address data received at a time switch control processor side is matched, converted into parallel data, and output in parallel. Data matching means for converting and transferring the form data into serial mode / address data to the time switch control processor; a sub highway matching means for matching with the time switch device; and the sub highway matching means for inputting a control signal; Performs error detection and maintenance function generated during echo cancellation operation of internal or entire system by transmitting and receiving data, and maintenance means matching with FI (Fault Interface), and outputted from the data matching means according to input of control signal Receive data and match the sub highway A plurality of circuit packs including data processing means for controlling the operation of the means and an echo canceling operation control means for controlling the data processing means and the maintenance means in accordance with the data for the mode input to the data matching means. Echo cancellation can be performed on 64 channels per LECA by mounting 16 DSPs. When up to 16 echo cancellation circuit packs are mounted, echo cancellation or echo cancellation can be performed on 1024 channels.

Description

Telephone network multichannel echo canceller

1 is a simplified block diagram of a multi-channel echo cancellation device according to the present invention.

2 is a diagram illustrating the configuration of the echo cancellation circuit pack of FIG.

3 is a diagram illustrating the configuration of a TD-bus matching block of an echo cancellation circuit pack.

4 is an exemplary diagram of a form of data code.

5 is a diagram illustrating the configuration of a control block of an echo cancellation circuit pack.

6 is a diagram illustrating a configuration of a subhighway matching block of an echo cancellation circuit pack.

7 is a diagram illustrating the configuration of a maintenance block of an echo cancellation circuit pack.

* Explanation of symbols for main parts of the drawings

210: TD-bus matching circuit 220: dual port RAM

200: TD-bus matching block 310: control circuit

320: RS-232C match 300: control block

410-425: DSP 430: Boot EPROM

400: DSP block 500: subhighway matching block

600: Maintenance block 211: RS-485 receiver for TD-bus

212 RS-485 driver for TD bus 213 TD bus clock supervisory circuit

214: mode / address serial / parallel conversion circuit 215: mode / address decoder

216: generating circuit 220: dual port RAM

217: dual port RAM control circuit 218: data bottle / serial conversion circuit

220: dual port RAM 311: 1-chip controller

312 latch circuit 313 decoder

314: reset circuit 320: RS-232C matching

510: RS-485 receiver for subhighway 520: RS-485 driver for subhighway

530: subhighway clock supervisory circuit 540: multiplexer

550: counter 610: error collection circuit

620: hernia monitoring circuit 630: feedback circuit

The present invention relates to an echo canceller in a digital mobile telecommunication switch, and more particularly, to a telephone network multichannel echo canceller for removing echo generated when a digital mobile telecommunication switch interoperates with a conventional notary communication network (PS number). will be.

Often, reverberation in a telephone network refers to a phenomenon in which a clear or unclear call is repeated for a caller or a sign language through a path other than the intended channel.

The main cause of such reverberation is due to impedance mismatch in the transmission path, especially in mobile communication networks.

That is, when the voice of the mobile subscriber is transmitted to the fixed subscriber via the public telephone network (PS number), the impedance mismatch occurs because there is a two-wire or four-wire hybrid circuit on the public telephone network side.

In particular, since the digital mobile communication exchange performs voice coding to increase the efficiency of the wireless channel, there is a delay of about 90 dB in one-way, and the echo returned to the subscriber is accompanied by a delay of about 200 dB including the pure channel delay. The user has a problem that the user feels uncomfortable with the call.

An object of the present invention for solving the above problems is to install the PCM voice data output from the digital mobile communication switch by interlocking with a time switch device for receiving a relay line connected to the digital mobile communication switch network and the existing public telephone network The echo canceller receives the same data and transmits it to the digital filter in the echo canceller to estimate the impulse response of the delay and echo of the path through the 2-wire and 4-wire hybrids of the public telephone network. The present invention provides a telephone network multichannel echo canceller for removing echoes from a public telephone network by subtracting a signal from data from a public telephone network.

A feature of the present invention for achieving the above object is, in the telephone network multi-channel echo cancellation device for canceling the echo generated when the digital mobile communication switch and the existing public communication network (PS number) interworking, the time switch control processor side Matches the serial mode / address data received from the controller, converts the parallel mode data into parallel data, and converts the parallel data input from the output side into the serial mode / address data to the time switch control processor. Means, sub-highway matching means to be matched with the time switch device, and data to and from the subhighway matching means according to the input of a control signal to perform error detection and maintenance functions generated during echo cancellation operation of the internal or entire system. Maintenance means that match the FI (Fault Interface) and control signals The data processing means and the maintenance means according to data input means for receiving the data output from the data matching means and controlling the operation of the subhighway matching means and data for the mode input to the data matching means. It includes a plurality of circuit packs having an echo canceling operation control means for controlling.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a simplified block diagram of a multi-channel echo canceller according to the present invention, which is comprised of an echo cancellation circuit pack capable of selectively mounting one to sixteen tickets according to system capacity and a back board accommodating these circuit packs. .

Looking at the configuration of the echo cancellation circuit pack, which is the main part of the present invention, with reference to the accompanying Figure 2, it can be divided into five blocks according to the functional form for each circuit, TD-bus (Telephony Device-bus) Control including TD-bus matching block 200 composed of matching circuit 210 and dual port RAM 220, control circuit 310 composed of 1-chip controller and peripheral circuit, RS-232C matching 320 A block 300, a DSP block 400 consisting of 16 DSPs 410 to 425, a boot EPROM 430, a subhighway matching block 500 that matches the time switch device, an echo cancellation circuit pack or echo It consists of a maintenance block 600 that performs error detection and maintenance functions of the removal device and is matched with a FI (Foult Interface).

The configuration of the TD-bus matching block is as shown in FIG. 3, wherein the echo cancellation circuit pack controls the time-switch when the data is sent to and received from the time switch control processor (TSP) and the TD-bus. In contrast to the RS-485 receiver 211 for the TD bus, which converts the signal and data of the differential level received from the processor into the T-time level for convenient use in the echo cancellation circuit pack, the differential signal and data of the T-time level RS-485 driver 212 for the TD bus which converts the level to the time switch control processor, receives the TD bus clock supervisor circuit 213 for checking the state of the TD bus clock, and receives it from the time switch control processor. A mode / address serial / parallel conversion circuit 214 for converting a serial mode / address signal into a parallel form, and a mode / address for generating a necessary signal by reading a mode / address signal converted in parallel. Time switch control processor is ready to send and receive data from the echo cancellation circuit pack of the 16 echo cancellation circuit packs in the echo cancellation device by inputting the address decoder 215 and the address signal of the mode / address decoder 215 as input. Informed A generation circuit 216 for generating a signal and a signal for converting serial data from the time switch control processor into a parallel form and storing the data in the dual port RAM 220 may be generated. Dual-port RAM control circuit 217 for generating a signal for sending data stored in the 220 to the time switch control processor, and in parallel form so that the data stored in the dual port RAM 220 can be extracted and transmitted to the time switch control processor. A data bottle / serial conversion circuit 218 for converting data into a serial form, and a dual port RAM 220 serving as a buffer to facilitate communication between the time switch control processor and the echo cancellation circuit pack.

The main function of the TD-bus matching block 200 of the echo cancellation circuit pack shown in FIG. 3 receives serial mode / address information having a format similar to that of FIG. Form, analysis, and corresponding echo cancellation circuit pack It generates a signal and receives a control command from the time switch control processor or transmits status information of the echo cancellation circuit pack to the time switch control processor.

5 is a block diagram of the control block 300 of the echo cancellation circuit pack. The chip controller 311 and the chip controller 311 which control the echo cancellation circuit pack control the 16 DSPs. A latch circuit 312 composed of a plurality of latches and peripheral circuits, a decoder 313 for enabling a corresponding latch in the latch circuit 312 by inputting an address of the one-chip controller 311, and an echo canceling circuit pack are reset. A reset circuit 314, and an RS-232C match 320 that causes the state of the echo cancellation circuit pack to appear on the CRT terminal.

The control block 300 controls the DSP and the peripheral circuits according to the control information received from the time switch control processor to perform the echo cancellation function or to stop the echo cancellation function in progress. I am responsible for reporting to the FI.

The one-chip controller 311 stores the firmware in ROM and RAM built in the one-chip controller 311 and operates by the firmware.

By using a latch that acts as a buffer between the one-chip controller 311 and the DSP, the difference in data size and speed between the one-chip controller and the DSP is overcome, and the bus arbitration function required for one-to-n communication is also solved. Communication between the 311 and a plurality of DSPs was made smoothly.

FIG. 6 is a block diagram of the subhighway matching block 500 of the echo cancellation circuit pack. FIG. 6 is a diagram illustrating data generated when multiple DSPs perform echo cancellation and transmit data to a time switch device through a serial port of a DSP. It prevents collisions and prevents a faulty DSP from affecting data transfer over another DSP's serial port.

Sub-highway matching block 500 for this purpose is a sub-highway RS-485 receiver 510 for receiving and converting the sub-highway clock and PCM data received from the time switch device from the differential level to the T-time level, reverse echo cancellation The subhighway clock received through the RS-485 driver 520 for subhighway and the RS-485 receiver 510 for converting the PCM voice data removed by the circuit pack from the T-time level to the differential level conversion and transmitting them to the time switch device. A sub-highway clock monitoring circuit 530 for monitoring the state, a multiplexer 540 for adjusting the temporally canceled echo of PCM voice data transmitted from 16 DSPs to a time switch device so as not to cause a collision, and an RS-485 receiver The counter 550 is configured to provide a clock necessary for the multiplexer to operate properly by using the subhighway clock received through 510 as an input.

7 is a block diagram of the maintenance block 600 of the echo cancellation circuit pack. The error collection circuit 610 collects the errors of the TD-bus clock and the subhighway clock and the errors of the echo cancellation circuit pack and transmits them to the FI. In order to prevent interruption of a call made through the hernia monitoring circuit 620 for monitoring the hernia of the echo cancellation circuit pack and the hernia removal circuit pack during hernia removal, the PCM was subjected to the echo removal circuit pack. It consists of a loop-back (630) to prevent the interruption of the call by allowing the path of the voice data to pass through the adjacent echo cancellation circuit pack.

Referring to the function and operation of the present invention based on the configuration as described above, each echo cancellation circuit pack of the echo cancellation apparatus is initialized by power on or reset, under the control of the control block 300 of the echo cancellation circuit pack. Sixteen DSPs 410-425 sequentially download programs that perform echo cancellation from one boot EPROM 430 to the internal RAMs of DSPs 410-425.

If necessary, the status of the current LECA can be displayed on the monitor through RS-232C matching 320 to check the status. When the mobile subscriber's voice PCM data is transmitted to the relay line through a time switch device accommodating the relay line, the same data is also input through two 32-channel PCM subhighways to the echo cancellation circuit. Channels to be echo canceled through the serial ports of 410 to 417 are stored in each of the DSPs 410 to 417, and another subhighway is to be echo canceled through the remaining eight DSP (418 to 425) serial ports. The channel is transmitted to the FI via four channels to each of the DSPs 418 to 425.

The echo canceller according to the present invention operating as described above has 16 DSPs mounted on the echo canceller circuit pack, so that echo cancellation can be performed for 64 channels per LECA, and up to 16 echo canceller circuit packs are mounted. In 1024 channels, echo cancellation or echo cancellation can be performed for 1024 channels.

Claims (5)

A telephone network multichannel echo canceller for canceling echoes generated when a digital mobile telecommunication exchange is interworked with an existing public telecommunication network (PS number), wherein the serial mode / address data received from the time switch control processor is matched. Data matching means for converting and outputting data in parallel form and converting the parallel data inputted from the output side into serial mode / address data to the time switch control processor; Subhighway matching means for matching with the time switch device; Maintenance means for transmitting and receiving data to and from the subhighway matching means in accordance with an input of a control signal to perform error detection and maintenance functions generated during echo cancellation operation of an internal or entire system, and matching with a FI (Fault Interface); Data processing means for receiving data output from the data matching means in accordance with an input of a control signal and controlling the operation of the subhighway matching means; And a plurality of circuit packs including an echo canceling operation control means for controlling the data processing means and the maintenance means according to the data for the mode input to the data matching means. Device. 2. The apparatus of claim 1, wherein the data matching means comprises: a dual port RAM serving as a buffer to facilitate communication between the time switch control processor and an internal configuration; An RS-485 driver for a TD-bus for converting the signal and data of the differential level received from the time-switch control processor into a T-time level conveniently when using a TD-bus to exchange data with the time-switch control processor; On the contrary, an RS-485 driver for a TD bus for converting a signal and data of a T time level into a differential level and transmitting the same to the time switch control processor; A TD bus clock monitoring circuit for checking the state of the TD bus clock; A mode / address serial / parallel conversion circuit for converting a serial mode / address signal received by the time switch control processor into a parallel form; A mode / address decoder for reading a mode / address signal converted in parallel and generating a required signal; Inputting the address signal of the mode / address decoder, the time switch control processor is informed that it is ready to send and receive data of the corresponding echo canceller circuit pack among the 16 echo canceller circuit packs in the echo canceller. A signal generation circuit for generating a signal; It converts the serial data coming from the time switch control processor into the parallel form and generates a signal for storing the data in the dual port RAM 220, and sends the data stored in the dual port RAM 220 to the time switch control processor. A dual port RAM control circuit for generating a signal for sending; And a data bottle / serial conversion circuit for converting the parallel data into a serial form so as to extract data stored in the dual port RAM 220 and transmit the data to the time switch control processor. . The apparatus of claim 1, wherein the echo canceling operation control means comprises: a one-chip controller for controlling internal components; A latch circuit comprising a plurality of latches and peripheral circuits necessary for the one-chip controller to control the data processing means; And a decoder configured to enable a corresponding latch in the latch circuit by inputting an address of the one-chip controller. The subhighway matching means according to claim 1, further comprising: a sub-highway RS-485 driver for converting the subhighway clock received from the time switch device from the differential level to the T-time level; A sub-highway RS-485 driver for converting the PCM voice data removed by the echo cancellation circuit pack from the TTL level to the differential level and transmitting the differential level to the time switch device; A subhighway clock monitoring circuit for monitoring a state of the subhighway clock received through the RS-485 driver; A multiplexer which adjusts the echo canceled PCM voice data sent from 16 DSPs to a time switch device in a timely manner so that a collision does not occur; And a counter providing a clock necessary for the multiplexer to operate properly by inputting the subhighway clock received through the RS-485 driver. 2. The apparatus of claim 1, wherein the maintenance means comprises: an error collecting circuit unit configured to collect an error of a TD-bus clock and a subhighway clock and an error of an echo cancellation circuit pack and transmit the error to an FI; Hernia monitoring circuit unit for monitoring the hernia of the echo cancellation circuit pack; In order to prevent interruption of a call made through the mounted echo cancellation circuit pack when the echo cancellation circuit pack is dismounted, the PCM voice data routed through the mounted echo cancellation circuit pack passes through the adjacent echo cancellation circuit pack to stop the interruption. Telephone network multi-channel echo canceller, characterized in that consisting of a feedback to prevent.