KR970003219A - Delay time adjustment circuit - Google Patents

Delay time adjustment circuit Download PDF

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Publication number
KR970003219A
KR970003219A KR1019950016180A KR19950016180A KR970003219A KR 970003219 A KR970003219 A KR 970003219A KR 1019950016180 A KR1019950016180 A KR 1019950016180A KR 19950016180 A KR19950016180 A KR 19950016180A KR 970003219 A KR970003219 A KR 970003219A
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KR
South Korea
Prior art keywords
delay
value
register
delay time
time adjustment
Prior art date
Application number
KR1019950016180A
Other languages
Korean (ko)
Other versions
KR0164822B1 (en
Inventor
임우택
홍성민
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950016180A priority Critical patent/KR0164822B1/en
Publication of KR970003219A publication Critical patent/KR970003219A/en
Application granted granted Critical
Publication of KR0164822B1 publication Critical patent/KR0164822B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters

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  • Pulse Circuits (AREA)

Abstract

1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

지연타임 조정회로에 있어 지연타임 조정값을 레지스터에 저장하여 이로부터 출력되는 값에 의해 지연타임 값을 조정함.In the delay time adjustment circuit, the delay time adjustment value is stored in a register and the delay time value is adjusted by the value output from it.

2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention

상기 공정상에서의 문제, 테스트시에 딜레이값의 변화에 따른 테스트 패턴의 패턴의 변화로부터 정확한 딜레이 값을 얻기 위해 각단의 레지스터를 이용하여 상기 레지스터에 설정되는 값에 따라 딜레이 체인의 값을 조정하여 줌으로서 공정상의 변화와 테스트시에 발생되는 변수에 대해 레지스터의 설정 값을 변화시켜 원하는 딜레이 값을 얻을 수 있는 회로를 제공함.The delay chain is adjusted according to the value set in the register using registers at each stage in order to obtain an accurate delay value from the problem in the process and the pattern of the test pattern according to the change in the delay value during the test. It provides a circuit that can obtain the desired delay value by changing the setting value of the register with respect to process changes and variables generated during the test.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

n비트의 공정상의 변화와 테스트시에 사용되는 딜레이 조정 데이타 값을 보관하고 있는 레지스터부(200)와, 상기 레지스터부(200)의 각 레지스터(RG0-TGN)에 할당된 값에 따라 지연값이 조절되는 n개의 지연체인(200~208)으로 구성됨.Delay according to the value assigned to each register (RG 0 -TG N ) of the register section 200 which stores n-bit process changes and the delay adjustment data value used in the test. It consists of n delay chains (200 ~ 208) whose values are adjusted.

4. 발명의 중요한 용도4. Important uses of the invention

지연타임 조절회로.Delay time control circuit.

Description

지연 타임 조정회로Delay time adjustment circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 회로2 is a circuit according to the present invention.

Claims (4)

지연회로에 있어서, n비트의 데이타값을 보관하고 있는 레지스터(200)와, 상기 레지스터(200)의 각 레지스터(RGO~RGN)에 할당된 값에 따라 지연값이 조절되는 n개의 지연체인(200~208)으로 구성됨을 특징으로 하는 지연타임 조정회로.In the delay circuit, n delay bodies whose delay values are adjusted in accordance with registers 200 that hold n-bit data values and values assigned to each register (RG O to RG N ) of the register 200. Delay time adjustment circuit, characterized in that consisting of (200 ~ 208). 제1항에 있어서, 상기 지연체인들(200~208)중 적어도 하나의 지연체인은 각 레지스터(RGO~RGN)의 출력단에 입력포트(101)로 입력되고 입력신호를 지연할 것인지 지연을 안시킬 것인지를 선택회로 선택수단과 상기 선택수단의 출력에 의해 상기 입력포트(101)의 입력신호를 지연없이 직접 통과시키는 제어신호 전달수단과, 상기 입력포트(101)의입력신호에 대해 상기 각 레지스터(RG0~RGN)의 출력에 의해 전달하기 위한 제2신호 전달 수단과, 상기 제2신호 전달수단에 포함되어 있으며, 상기 입력포트(101)의 입력신호를 소정지연 하는 지연수단으로 구성됨을 특징으로 하는 지연타임 조정회로.The delay chain of claim 1, wherein at least one delay chain of the delay chains 200 to 208 is input to the input port 101 at an output terminal of each register RGO to RGN, and does not delay the input signal. Control signal transmission means for directly passing an input signal of the input port 101 without delay by means of a selection circuit selection means and an output of the selection means, and for each input signal with respect to the input signal of the input port 101; A second signal transmission means for transmitting by the output of RG0 to RGN, and delay means for delaying an input signal of the input port 101, which is included in the second signal transmission means. Delay time adjustment circuit. 제2항에 있어서, 선택수단이 인버터로 구성됨을 특징으로 하는 지연타임 조정회로.3. The delay time adjustment circuit as claimed in claim 2, wherein the selection means comprises an inverter. 제2항에 있어서, 제1도는 제2신호전달수단이 3-스테이프 버퍼로 구성됨을 특징으로 하는 지연타임 조정회로.3. The delay time adjustment circuit as set forth in claim 2, wherein the second signal transmission means is constituted by a three-step buffer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950016180A 1995-06-17 1995-06-17 Delay time control circuit KR0164822B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950016180A KR0164822B1 (en) 1995-06-17 1995-06-17 Delay time control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950016180A KR0164822B1 (en) 1995-06-17 1995-06-17 Delay time control circuit

Publications (2)

Publication Number Publication Date
KR970003219A true KR970003219A (en) 1997-01-28
KR0164822B1 KR0164822B1 (en) 1999-02-01

Family

ID=19417428

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950016180A KR0164822B1 (en) 1995-06-17 1995-06-17 Delay time control circuit

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KR (1) KR0164822B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100605512B1 (en) * 2005-02-14 2006-07-28 삼성전자주식회사 Semiconductor memory device and memory system comprising the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100605512B1 (en) * 2005-02-14 2006-07-28 삼성전자주식회사 Semiconductor memory device and memory system comprising the same

Also Published As

Publication number Publication date
KR0164822B1 (en) 1999-02-01

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