KR970003120A - Interface device in digital video cassette recorder - Google Patents
Interface device in digital video cassette recorder Download PDFInfo
- Publication number
- KR970003120A KR970003120A KR1019950018634A KR19950018634A KR970003120A KR 970003120 A KR970003120 A KR 970003120A KR 1019950018634 A KR1019950018634 A KR 1019950018634A KR 19950018634 A KR19950018634 A KR 19950018634A KR 970003120 A KR970003120 A KR 970003120A
- Authority
- KR
- South Korea
- Prior art keywords
- signal
- cassette recorder
- write
- video cassette
- reset
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/91—Television signal processing therefor
- H04N5/911—Television signal processing therefor for the suppression of noise
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
- H04N5/775—Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television receiver
Abstract
본 발명은 디지탈 비디오 카세트 레코더에서의 인터페이스 장치에 관한 것으로서, 이를 위하여, 셋탑 박스(Set TopBox)(100)와 비디오 카세트 레코더(Video Cassette Recorder)(300)를 인터페이스시키는 장치로서, 입력되는 디지탈 데이타 비트 스트림에서 검출한 동기 신호와 디지탈 비디오 카세트 레코더(300)로부터의 드럼 위상 신호에 따라 리셋 신호와제 1, 2 기록/판독 인에이블 신호를 선택적으로 발생하는 인에이블 신호 발생부(210)와, 상기 인에이블 신호 발생부(210)로부터의 리셋 신호에 따라 리셋되고 디지탈 데이타 비트 스트림에서 복구된 클럭 신호에 따라 기록 주소 신호를 발생하는 제 1 주소 발생부(220)와; 상기 인에이블 신호 발생부(210)로부터의 리셋 신호에 따라 리셋되고 비디오 카세트 레코더(300)로부터의 기록 속도에 대응하는 클럭 신호에 따라 판독 주소 신호를 발생하는 제 2 주소 발생부(250)와; 상기 제 1기록 인에이블 신호에 의해 기록 인에이블되고 입력되는 디지탈 데이타 비트 스트림이 상기 기록 주소 신호에 의거하여기록되며, 상기 제 1 판독 인에이블 신호와 판독 주소 신호에 의거하여 기록된 디지탈 데이타 비트 스트림을 디지탈 비디오 카세트 레코더로 출력하는 제 1 메모리 (230)와; 상기 제 2 기록/판독 인에이블 신호와 기록 주소 신호와 판독 주소신호에 의거하여 상기 제 1 메모리(230)와 번갈아 가며 디지탈 데이타 비트 스트림을 기록 및 출력하는 제 2 메모리(240)를 포함하는 디지탈 비디오 카세트 레코더에서의 인터페이스 장치를 제공함으로써, 전송중에 발생되는 지터 잡음에 의한 에러를 최소한으로 줄일 수 있는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface device in a digital video cassette recorder. To this end, an apparatus for interfacing a set top box (100) and a video cassette recorder (Video Cassette Recorder) 300 is provided. An enable signal generator 210 for selectively generating reset signals and first and second write / read enable signals in accordance with the synchronization signal detected in the stream and the drum phase signal from the digital video cassette recorder 300; A first address generator 220 which is reset according to a reset signal from the enable signal generator 210 and generates a write address signal according to a clock signal recovered from the digital data bit stream; A second address generator 250 which is reset according to the reset signal from the enable signal generator 210 and generates a read address signal according to a clock signal corresponding to a recording speed from the video cassette recorder 300; The digital data bit stream, which is write enabled and input by the first write enable signal, is written based on the write address signal, and is written based on the first read enable signal and the read address signal. A first memory 230 for outputting the digital video cassette recorder to the digital video cassette recorder; Digital video including a second memory (240) for alternately writing and outputting a digital data bit stream based on the second write / read enable signal and a write address signal and a read address signal. By providing the interface device in the cassette recorder, the error due to jitter noise generated during transmission can be minimized.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
본 도면은 본 발명의 바람직한 실시예에 따른 인터페이스 장치에 대한 블럭도.Figure is a block diagram of an interface device according to a preferred embodiment of the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950018634A KR0171139B1 (en) | 1995-06-30 | 1995-06-30 | Interface device for dvcr |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950018634A KR0171139B1 (en) | 1995-06-30 | 1995-06-30 | Interface device for dvcr |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970003120A true KR970003120A (en) | 1997-01-28 |
KR0171139B1 KR0171139B1 (en) | 1999-04-15 |
Family
ID=19419074
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950018634A KR0171139B1 (en) | 1995-06-30 | 1995-06-30 | Interface device for dvcr |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0171139B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100453965B1 (en) * | 2002-01-09 | 2004-10-20 | 엘지전자 주식회사 | Method And Apparatus for exchanging data between external device and TV set |
-
1995
- 1995-06-30 KR KR1019950018634A patent/KR0171139B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0171139B1 (en) | 1999-04-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR890017977A (en) | Video signal conversion device | |
KR900002647A (en) | Super Infos Device | |
KR970029615A (en) | Music information recording and playback method, playback device | |
KR860008549A (en) | Video player | |
KR850005934A (en) | Video signal processing device | |
KR940020375A (en) | Audio signal recording format and method and device | |
KR950034108A (en) | Servo address mark detection compensation circuit | |
KR870003660A (en) | Image memory control device of video signal reproduction system | |
KR920001486A (en) | Digital signal reproduction processing device | |
KR880003316A (en) | Write compensation circuit of magnetic disk device | |
KR890001066A (en) | Memory controller | |
KR970003120A (en) | Interface device in digital video cassette recorder | |
KR840002133A (en) | Data player | |
KR920022668A (en) | Digital Signal Processing Equipment | |
KR890010804A (en) | Reversing voice regeneration circuit | |
KR880005609A (en) | Code Error Correction Circuit | |
KR920015355A (en) | Optical Information High Speed Search System | |
KR910019022A (en) | Image signal processing method and device | |
KR920005066A (en) | Video signal playback device | |
KR960015170A (en) | Data Crosstalk Prevention Circuit of Image Memory | |
KR930001217A (en) | Semiconductor memory | |
KR910017360A (en) | Signal Processing Circuit of Digital Audio Tape Recorder | |
JP2697197B2 (en) | Digital audio equipment | |
KR900007167B1 (en) | Multiplexer control pulse generating circuit for the correction circuit of time axis | |
KR870002564Y1 (en) | Clock generating circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20020930 Year of fee payment: 5 |
|
LAPS | Lapse due to unpaid annual fee |