KR970002786B1 - Packet access unit - Google Patents

Abstract

A packet access apparatus is disclosed. The packet access apparatus comprises: a plurality of communication channel boards; and a packet bus access means(16) for interface between the plurality of communication channel boards and a packet bus, wherein the plurality of communication channel boards respectively include a coding and line connection means(11) for coding serial data, a first store means(13) for storing a program, a data link control means(12) for converting the serial data to parallel data and checking a desitination address, a second store means(15) for storing the parallel data and a logic process means(14) for outputting the stored parallel data. Thereby, the packet access apparatus may improve the communication channel capacity.

Description

Packet connection device

1 is an overall configuration diagram of a packet switching system to which the present invention is applied.

2 is a block diagram of a packet access apparatus according to the present invention.

3 is a timing diagram for simulation results of the present invention.

* Explanation of symbols for main parts of the drawings

11 coding and line connection unit 12 HDLC processing unit

13 memory unit 14 logic processing unit

15: packet data storage unit 16: packet bus connection unit

The present invention relates to a packet access device for implementing a packet switching function in a large communication system such as a data communication device, a mobile communication base station device or a switching device.

When configuring a packet access device for packet switching in a general communication system, software processing is excluded as much as possible to meet the required data processing capacity and data processing speed.

Therefore, a considerable difficulty appears in the testing and self-management of the packet access device. In particular, when a communication protocol protocol processing function is to be performed, a separate method has to be considered.

In addition, in order to support various types of communication protocols and the form of data encoding when a packet connection device performs serial communication, communication that can be accommodated in a board, which is a minimum physical unit that constitutes a system when adopting necessary components The channel is restricted.

Accordingly, an object of the present invention is to provide a packet access apparatus for accommodating high-speed data processing, protocol processing, and various encoding forms in a data communication apparatus, a mobile communication base station apparatus, or a switching apparatus that requires a packet switching function.

In order to achieve the above object, the present invention provides an encoding and line connecting means for decoding serial data input from the outside connected to an external serial communication line, encoding and outputting data to be output to the serial communication line, and a processing procedure. A first storage means for storing a program representing a; and a program stored in the first storage means, receiving serial data decoded from the encoding and line connecting means, converting the serial data into parallel data, and converting a destination address of the received data. High level data link control means for confirming, second storage means for storing data transmitted and received with the high level data link control means, and control signals for data transmission and reception between the high level data link control means and the second storage means. Outputs the data to the second storage means when the right to use the packet bus is obtained. It transmits a control signal for transmitting the stored data, and a plurality of communication channel boards each having logic processing means for performing an error verification function according to data transmission and reception and the interface between the plurality of communication channel boards and the packet bus It is characterized by comprising a packet bus connection means in charge.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is an overall configuration diagram of a packet-switching system to which the present invention is applied, in which 1 denotes a packet controller, 2 a packet connection device, 3 a packet bus, 4 a packet bus connection, and 5 a communication channel.

The packet controller 1 performs a maintenance and management function of the entire packet switching system shown in FIG. 1, and performs a packet control function that allows multiple packet connection devices to sequentially exchange packet data with each other.

By having four communication channels, the packet connection device 2 can be connected with four serial communication lines, and data received from these serial lines can be transmitted to another packet bus connection device through the packet bus. The packet data conversion process is performed in the communication channel 5 and the packet bus connection section 4 which exist.

The packet bus 3 performs a passage function in which data exchange can be performed between the packet connection devices 2 under the control of the packet controller 1.

2 is a block diagram of a packet access device 2 according to the present invention, which includes an encoding and line connection unit 11, an HDLC processing unit 12, a memory unit 13, a logic processing unit 14, and a packet data storage unit ( 15) and a packet bus connection portion l6.

The encoding and line connecting portion 11 encodes the serial data to be transmitted to the outside via the serial communication line and the function of connecting with the line between the serial communication line outside the apparatus and the internal HDLC processing unit 12, and vice versa. Decrypt the serial data received over the communication line.

In the packet connection device 2, encoding can be performed by E1 encoding or T1 encoding, and may not perform any encoding.

If the user selects E1 or T1 encoding, Crystal and CS61574 use the encoding and E1 / T1 line connection functions. If no encoding is performed, only the line connection function is processed by National's DS76174 and 76175.

The high-level data-link control (HDLC) processing unit 12 is composed of Hitachi's HD64180S, and performs a function of converting serial data input from the encoding and line connection unit 11 into parallel data. do. Also, protocol processing and generation for serial communication, confirmation of destination address included in serial data, maintenance of corresponding communication channel in packet connection device, etc. Perform control.

The memory unit 13 stores program contents to be executed by the HDLC processing unit 12, and is composed of 27C128 which is a 16Kbyte ROM (ROM) of AMD.

The logic processor 14 is composed of EPLD5192, which is a device for the CUSTOM integrated circuit (IC) of ALTER, and performs a control function for transmitting and receiving packet data and an error verification function for transmitting and receiving data.

That is, the control signal for storing the data processed by the HDLC processing unit 12 to the packet data storage unit 15 is output, and vice versa, the data stored in the packet data storage unit 15 is transferred to the HDLC processing unit 12. Outputs a control signal for output.

When the use of the packet bus is permitted by the packet bus arbiter through the packet bus connection unit 16, a control signal for transmitting data stored in the packet data storage unit 15 to the packet bus is sent to the packet data storage unit 15. Output

The logic processing unit 14, EPLD5192, is a logic device capable of internally integrating approximately 6000-8000 gates, which accommodates a large amount of logic, and thus provides four communication channels despite the fact that the present packet bus connector has an encoding function. I can accept it.

The packet data storage unit 15 is composed of four IDT7202, IDT's First In First Out (FIFO) type memory, each of which is a FIFO for transmission tag storage, a FIFO for transmission data, a FIFO for reception tag storage, and reception. It acts as a FIFO for data storage. That is, before the data processed by the HDLC processing unit 12 is sent to the packet bus, the data storage function is performed until the current communication channel uses the packet bus. In addition, by adopting the tag FlFO separately, the tag bit width can be up to 9 bits to increase data reliability.

The packet bus connection unit 16 is composed of ALTERA's EPLD7192, and performs the function of distributing and controlling the packet bus usage rights for four communication channels in the packet bus connection unit.

3 is a timing diagram when the HDLC processing unit 12 transmits data to the packet data storage unit 15. In this case, the write (WRITE) command and the tag generation command of the packet data storage unit 15 are the logic processing unit ( 14).

In the case of (a) of FIG. 3, the HDLC processing unit 12 detects that the data is sent to the packet data storage unit l5. At this point, the HDLC processing unit 12 receives the packet data storage unit 15. The data is stored in.

In the case of (b) in FIG. 3, the HDLC processor 12 prepares to send data of a new packet (one packet may consist of several bytes), that is, the first byte of one packet, to be sent. At this time, when the WRITE command is detected, the tag 14 generates a tag value for data verification, and stores the tag value in the tag FIFO and transmits it to the packet bus separately from the packet data transmitted by the HDLC processor 12. Get ready.

Therefore, the present invention configured and operated as described above can obtain the following effects by applying to a packet access device when packet exchange is to be performed in a general communication system.

First, while maintaining the software processing function, protocol processing function, and maintenance function in the packet access device, it is possible to prevent the degradation of performance and data processing speed.

Second, by adopting a tag processing FIFO separately, it is possible to apply a tag of a plurality of bits, thereby increasing the reliability of data verification, and various classifications of data types are possible.

Third, by adopting HD64180S which has general control function along with HDLC processing function while selecting E1 / T1 coding and non-coding, it is possible to apply EPLD5192 and 7192 to increase the density. It is possible to improve the communication channel capacity in the connection device.

Claims (2)

An encoding and line connecting means (11) for decoding serial data input from the outside connected to an external serial communication line, encoding and outputting data to be output to the serial communication line, and a program indicating a processing procedure; 1 storing means 13 and a program stored in the first storing means 13, receiving serial data decoded from the encoding and line connecting means 11, converting the serial data into parallel data, and receiving the destination of the received data. High level data link control means 12 for checking an address, second storage means 15 for storing data transmitted and received with the high level data link control means 12, and the high level data link control means 12; And a control signal for transmitting and receiving data of the second storage means 15, and when the authority to use the packet bus is obtained, the data stored in the second storage means 15 A plurality of communication channel boards each having logic processing means 14 for transmitting a control signal for transmitting another and performing an error verification function according to data transmission and reception, and between the plurality of communication channel boards and the packet bus. And a packet bus connecting means (16) for handling the interface. 2. The apparatus of claim 1, wherein the second storage means is controlled by the logic processing means, and transmits a first FIFO (First In First Out) for storing data to be transmitted to the packet bus connection means, and controls the logic processing means. A transmission tag FIFO for storing a transmission tag for error verification of data to be transmitted to the packet bus connection means, a reception FIFO for controlling data received under the control of the logic processing means, and storing the received data to the packet bus connection means. And a receiving tag FIFO under control of logic processing means and storing a tag received by the packet bus connecting means.