KR970002767B1 - Sram writing circuit for switch - Google Patents

Abstract

The SRAM writing circuit in a matching device of a full electronic exchange is provided with: a serial/parallel converter (10) inputting address signals (M/A0-M/A3) of serial data from a processor device to convert them to parallel data and then, outputting an address signal of them to an address modulating unit of the processor device; a mode decoder (11) inputting mode signals (MO-M3) output from the serial/parallel converter (10), and inputting a frame synchronous signal (FS) and a processor clock (PPCLK) to output an SRAM writing mode signal (SRWM); and an RDY signal generator (12) inputting the frame synchronous signal (FS) and the processor clock (PPCLK) from the processor device, inputting the SRAM writing mode signal (SRWM) from the mode decoder (11) to output a ready signal (RDY) and delayed RDY signal (RDY-D) and then, outputting the delayed RDY signal (RDY-D) to the processor device, and inputs the SRAM writing mode signal (SRWM) from the mode decoder (11), inputs the RDY signal and the delayed RDY signal from the RDY signal generator (12) and a clock signal (CP3) and a delayed clock signal (CP3D) from a system clock distributor, and feedbacks its own output to input it and then, outputs a writing allowable signal to the SRAM.

Description

SRAM Write Circuit in Switch Matching Device of Electronic Switching System

1 is a peripheral circuit diagram of a memory SRAM for reading / writing to a transmission memory (SRAM) of a switching matching device.

2 is a timing diagram of an address bus and a data bus in FIG.

3 and 4 are timing diagrams for storing data from a processor device in an SRAM unit.

5 is a waveform diagram of the writeable time during the write allowance time in the write mode.

6 is a waveform diagram of a writable signal according to the present invention.

7 is a transition state diagram for the implementation of FIG.

8 is a block diagram of a conventional SRAM write circuit.

9 is a block diagram of an SRAM write circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

10: serial / parallel converter 11: mode decoder

l2: RDY signal generator 13,13 ': PAL (ProgramabIe Array Logic)

The present invention relates to an SRAM write circuit in a switch matching device of an all-electronic switch in which the switch matching device of the all-electronic switch stores data from the processor device into the SRAM of the switch matching device.

In an electronic switching system, a switch matching device has a function of receiving 1024 channels of serial data from a time division switching device, converting the serial data into 8 bits in parallel, and then transmitting the same to the spatial division switching device. The method for testing the data transmitting / receiving function of the switch matching device includes any test data generated in the processor device by the test program in the transmission memory (SRAM) of the switch matching device, and the test data read sequentially from the transmission memory is the switch. It is sent to the multiplexer of the matching device.

Specifically, FIG. 1 is a peripheral circuit diagram of a memory SRAM for reading / writing to a transmission memory (SRAM) of a switching matching device, in which 1 is an SRAM unit, 2 is a processor device address decoding unit, 3 represents the switching matching device address generating units, respectively.

The SRAM unit 1 is composed of 1024 x 8 SRAMs for testing 8-bit 1024 channels, and the SRAM unit 1 comprises a processor device address decoder 2 and a switch matching device address generator (1) through an address bus. 3) sends and receives data to and from the processor unit through the data bus and transmits the data to the switch matching unit multiplexer.

The timings of the address bus and the data bus are the same as those of the second diagram, in the figure, a is an address decoded after being received from the processor device, b is an address generated at the address generation unit of the switch matching device, and c is received from the processor device. The decoded data, d, then represent SRAM output data, respectively.

As shown in the figure, in the address bus, a memory read address generated to vary from 0 to 1023 for data transmission of sequential addresses, and a parallel converted address received from the processor device for writing, are 8.192. The half-cycle (61 ns) of the MHz (CP3) clock pulses are combined to form an address bus.

The SRAM unit 1, which is a data transmission memory, stores data from the processor unit in the SRAM unit 1 during a half cycle (61 ns) of 8.192 MHz (CP3) for a certain allowable time when receiving a data write (write) command from the processor unit. Then, the data of the SRAM unit 1 is read out by the address generated by the switch matching device address generation unit 3 for the remaining half period and sent to the multiplexing unit of the switch matching device.

In addition, the data bus is a portion for recording the data received from the processor device in the SRAM unit 1, a portion for the processor device to read the received data, and sending the data contained in the SRAM unit (1) to the multiplexing unit of the switch matching device. It consists of parts for

Timings for recording data from the processor device into the SRAM unit 1 are the same as those in FIGS. 3 and 4.

When the frame registration signal (FS), the processor clock (PPCLK) mode, and the address signal (M / A) are received from the processor device, the switch matching device decodes the mode and address signals and at the same time has a ready pulse width equal to the FS signal. Sends the RDY signal to the processor unit. Then, after a half cycle (400ns) of 1.25MHz of the RDY signal, 8-bit data is transmitted in series from the processor device, and the switch matching device converts it to 8-bit parallel data and prepares the occupancy on the data bus of the SRAM unit 1. do. At this time, if the SRAM unit 1 write mode is designated from the mode decoding (SRAM unit 1 write mode signal SRWM = "0 ''), the actual write is performed after the RDY signal is extinguished (" 0 "to" 1 "). 1.25MHz is performed for one period (800ns), and since the write cycle of the writeable signal is 122ns, the same data is repeatedly written to the same address 6-7 times.

Here, the SRWM (SRAM write mode) signal receives and decodes the FS, PPCLK, and mode signals M0 to M3 from the processor device, and then decodes the SRAM write modes (M3, M2, Ml, M0 = '' 1, 1, 0, 1 "), it transitions to '' 0 '' and indicates that the SRAM write mode is entered.

The RDY signal decodes the MO to M3 signals received from the processor device and then, when the SRAM write mode of the switch matching window is in the SRAM write mode, informs the processor device that the SRAM is ready for writing. The RDY signal is delayed by about 10 times with the PPCLK signal. Send to the processor unit. The RDY-D signal is a signal required for making the time signal for the SRAM write mode, and is delayed by the PPCLK signal period (800 ns) than the RDY signal.

CP3 and CP3D are signals generated by the system clock distribution device and received by the switch matching device. The CP3 is an 8.192 MHz clock signal, and the CP3D is an 8.192 MHz clock signal having a phase delay of 30.5 ns (30.5 ns) from the 8.192 MHz clock.

In this circuit, the 8.192 MHz clock at the switch matching device is the clock received at the system clock distribution unit, and the 1.25 MHz clock received at the processor unit is the clock oscillated inside the processor unit, so the 8.192 MHz clock and l.25 MHz clock are Are asynchronous to each other.

Therefore, in the write mode, the waveform of the writeable time during the write allowance time (800 ns) has two cases as shown in (a) and (b) of FIG. 5. That is, the waveform of the writable signal SRWE may be performed exactly six times in 800 ns and may be performed seven times.

Here, the writable signal (/ SRWE) = / SRWM, CP3, / CP3D, RDY, / RDY-D, and the write permission signal consists of the / SRWM, RDY, / RDY-D signals, and the meaning of this signal is defined in this section. SRAM write means possible.

The CP3 / CP3D signal, which is a logical product of CP3 and / CP3D, has a pulse width of 30.5 ns and SRAM write is performed only during this pulse width. Therefore, the SRAM writable signal consists of the signals / SRWM, RDY, RDY-D, CP3, and CP3D, which indicates that the same data is repeatedly written 6-7 times at the same address for 800 ns. The reason for this sparse repetitive write over 800ns is that the SRAM output data must be continuously loaded onto the data bus during the 8.192MHz half cycle.

However, in order to normally record certain data in the SRAM unit 1, a writable signal having a constant pulse width in accordance with the characteristics of the SRAM unit 1 is required. However, as shown in (b) of FIG. 5, a case in which the period of the seventh writable signal does not satisfy the minimum pulse width required by the SRAM unit 1 may occur. In such an unstable state, the SRAM unit 1 may be unstable. In some cases, normal data may be written depending on the characteristics, and data may not be written so that data that was written at the sixth writable signal may be retained. However, this may not be a problem.

However, when such data is unsuccessful in attempting to write data to the SRAN 1 unit 1, there is a problem that the wrong data is finally written to the SRAM unit 1.

Accordingly, an object of the present invention is to provide a write circuit for accurately performing an SRAM write operation in a switch matching device of an electronic switch.

In order to achieve the above object, the present invention provides a serial / parallel conversion unit which receives a mode and address signal which is serial data from a processor device and converts the data into parallel data, and outputs an address signal to the processor device address decoding unit. A mode decoder configured to receive a mode signal output from the parallel converter, a frame decoder and a processor clock from the processor device, and output a SRAM write mode signal, a frame synchronizer signal and a processor clock from the processor device; In the switch matching device of the electronic switchboard having an RDY signal generation unit for receiving the SRAM write mode signal from the mode decoding unit and outputting a ready (RDY) signal and a delayed RDY signal, and outputting a ready (RDY) signal to the processor device. In an SRAM write circuit, an SRAM is written from the mode decoder. Inputs the RAD signal, the RDY signal and the delayed RDY signal from the RDY signal generator, receives the clock signal and the delayed clock signal from the system clock distribution device, feeds its own output and receives the write permission signal into the SRAM. Output.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

6 is a waveform diagram of a writable signal according to the present invention, the writable signal / SRWE = / SRWM / RDY / RDY-D / CP3 / CP3D + / SRWM / CP3 / CP3D / SRWE according to the present invention. The seventh writable signal is equal to the pulse width of another writable signal.

Figure 7 also shows the transition state diagram for the implementation of Figure 6, where the inputs are A, B, C, where A = SRWM, B = RDY · RDY-D, C = CP3 · CP3D, and ''- '' Is don't care.

8 is a block diagram of a conventional SRAM write circuit, where reference numeral 10 is a serial / parallel converter, code 11 is a mode decoding unit, code 12 is an RDY signal generator, and code 13 is RAL is shown respectively.

As shown in the figure, the SRAM write circuit according to the prior art receives serial data in mode and address signals M / A0 to M / A3 from a processor device and converts them into parallel data, among which the address signal is a processor device. The serial / parallel converter 10 outputting the address decoder and the mode signals M0 to M3 output from the serial / parallel converter 10 are input, and the frame registration signal FS and the processor clock are received from the processor device. A mode decoder 11 for receiving PPCLK and outputting an SRAM write mode signal SRWM, a frame synchronization signal FS, and a processor clock PPCLK from a processor device, and from the mode decoder 11 An RDY signal generator 12 for receiving the SRAM write mode signal SRWM and outputting the RDY signal and the delayed RDY signal RDY-D, and outputting the delayed RDY signal RDY-D to the process device; Write SRAM from Decoder 11 A mode signal SRWM is input, a RDY signal and a delayed RDY signal RDY-D are input from the RDY signal generator 12, and a clock signal CP3 and a delayed clock signal CP3 are received from a system clock distributor. It is provided with a PAL (13) for receiving a and outputting the write permission signal (SR 'VND) to the SRAM.

Here, / SRAM = / SRWM CP3 / CP3d RDY / RDY-D by the operation logic of the PAL 13. However, such a conventional circuit has the problems described above, and the circuit of the present invention for solving this problem is the same as the ninth degree.

The same reference numerals as in FIG. 9 to FIG. 8 denote the components in FIG. 8, and 13 'is a PAL having an operational logic according to the present invention.

As shown in the drawing, the SRAM write circuit according to the present invention, in the configuration of FIG. 8, replaces the PAL 13 with a PAL (feedback) of the write permission signal SRWE, which is its output, to receive an additional input as an input signal. 13 ').

The operation logic of the PAL 13 'according to the present invention is / SRWE = / SRWM · RDY · / RDY-D · CP3 · / CP3D + / SRWM · CP3 · / CP3D · / SRWE.

According to the present invention, as shown in FIG. 8, the SRWM signal is " l " (when not in SRAM write mode) or the SRWM and RDY / RDY-D signals are respectively " 0, 0 " Or (when SRAM write mode but not write time) SRWM, RDY / RDY-D and CP3 / P3D signals are '' 0,1,0 '' (SRAM write mode, write time, but write) When it is not timing to keep) The status ("1") is maintained and when the SRWM, RDY / RDY-D, and CP3 / CP3D signals are "0,1, l", respectively (SRAM write mode and write allow time) While it is timing to write), it is changed to `` 0 '' state.

When SRWE signal is "0", SRWM, RDY / RDY-D and CP3 / CP3D signals are '' 0,1,1 '' or `` 0,0,1 '' (SRAM write mode, write allow time, respectively) In this case, it is the timing to write) or (in the SRAM write mode, but the timing to write even if the writing time is not allowed) and the status is changed to '' 1 '' otherwise.

In this case, after the 7th SRWE signal is changed to '' 0 '', the RDY / RDY-D (write allowable time) signal is changed to "0" and "0" for the period of CP3 / CP3D signal after the write allow time is over. After changing to " 1 ", the state of the write enable signal always has a constant pulse width.

Therefore, in the present invention configured and operated as described above, the switch matching device always has the same writable signal width so that the writable signal having the pulse width required by the SRAM is always kept constant so that an accurate SRAM write operation is always performed. It is effective to make.

Claims (1)

A serial / parallel converter 10 which receives a serial date mode and an address signal (M / A0 to N / A3) from the processor device and converts the data into parallel data, and outputs the address signal to the processor device address / decoding unit; The SRAM write mode signal SR`VM receives the mode signals M0 to M3 output from the serial / arc converter 10, receives the frame synchronization signal FS and the processor clock PPCLK from the processor device. A frame decoding signal FS and a processor clock PPCLK from the processor decoding device 11 and a processor device, and an SRAM write mode signal SR'VM from the mode decoder 1l. Switching matching device of an electronic switchboard having an RDY signal generator 12 for outputting a ready RDY signal and a delayed RDY signal RDY-D, and outputting the delayed RDY signal RDY-D to a processor. In the SRAM write circuit in the above, The SRAM write mode signal SRWM is input from the decoding decoder l1, the RDY signal and the delayed RDY signal RDY-D are input from the RDY signal generator l2, and the clock signal CP3 is received from the system clock divider. And a delayed clock signal (CP3D), and feeds back its own output so as to output a write permission signal (SRWM) to the SRAM.