KR970001293Y1 - Private switching - Google Patents

Abstract

None.

Description

DTMF signal receiver of private exchange

1 is a block diagram of a DTMF signal receiving apparatus of a conventional private exchange.

2 is a block diagram of a DTMF signal receiving apparatus of a private exchange according to the present invention.

* Description of the main parts of the drawings

30: clock generator 31: combo circuit

32: DTMF receiver 33: three-state buffer

34,36: counter 35: inverter

37: memory 38: processor

The present invention relates to a private exchange, and more particularly, to a DTMF signal receiving apparatus of a private exchange to supply DTMF signal information input to the private exchange to the processor side quickly.

As shown in FIG. 1, the DTMF signal receiving apparatus of the conventional private exchange includes the clock generator 10, the combo circuit 11, the DTMF receiver 12, the inverters 13 and 17, the flip-flop 14, It is connected to the tri-state buffer 15, the counters 16 and 18, the quad flip-flop 19, the memory 20, and the processor 21. The clock generator 10 supplies a clock signal to the combo circuit 11 and the counter 16, and the counter 16 generates a synchronization signal according to the clock signal supplied from the clock generator 10 to generate an inverter ( 17) to the combo circuit 11 side. The combo circuit 11 converts the digital DTMF signal supplied from the highway HW into an analog DTMF signal according to the clock signal supplied from the clock generator 10 and the synchronization signal supplied from the counter 16. Output to the receiver 12 side.

The DTMF receiving unit 12 converts the analog DTMF signal supplied from the combo circuit 11 into the corresponding numeric data, outputs it to the quad flip-flop 19 side, and at the same time a high level for indicating that the numeric data is being output. -level) output status signal to the inverter (13). The counter 18 outputs a clear signal to the flip-flop 14 side according to the address signal supplied from the processor 21 via the address bus AB and the synchronization signal SI supplied separately, and the quad-flop flop 19 Output signal is output to the tri-state buffer 15 side at the same time.

The inverter 13 inverts the high level output state signal supplied from the DTMF receiver 12 and supplies it to the flip-flop 14 side as a clock signal and also to the quad flip-flop 19 side as a clock signal. The quad flip-flop 19 operates according to the enable signal supplied from the counter 18 and the clock signal supplied from the inverter 13 to convert the numeric data supplied from the DTMF receiver 12 into the data bus DB. Is output to the memory 20 side, and the memory 20 stores numerical data supplied from the quad flip flop 19. The flip-flop 14 outputs a high level signal to the tri-state buffer 15 when the signal supplied from the inverter 13 transitions from the low level to the high level, and the tri-state buffer 15 is the counter 18. When the output enable signal is supplied from, the high level signal supplied from the flip flop 14 is output to the processor 21. When the high-level signal is supplied from the tri-state buffer 15, the processor 21 recognizes that the DTMF receiver 12 is outputting numerical data, and addresses the memory 20 through the address bus AB. The numerical data stored in the memory 20 is read through the data bus DB for analysis.

As described above, since the DTMF signal receiving device of the conventional private exchange has a complicated circuit configuration, there is a problem that not only the productivity is lowered but also the cost is increased in circuit fabrication. There was a problem to increase.

The present invention has been devised in view of the above-described problems, and has a simple circuit configuration that can reduce the load on the system by improving productivity in circuit removal, reducing costs, and reducing DTMF signal processing time. An object of the present invention is to provide a DTMF signal receiving apparatus of an exchange.

In order to achieve the above object, the present invention provides a counter 34 for generating a synchronization signal according to a clock signal supplied from a clock generator 30, a clock supplied from the clock generator 30, and the counter. A combo circuit 31 for converting a digital DTMF signal from the system highway HW into an analog DTMF signal in accordance with the synchronization signal supplied from the inverter 35 through the inverter 35, to the address signal and the synchronization signal S2. The counter 36 outputs an enable signal, and converts the analog DTMF signal into numeric data according to the enable signal supplied from the counter 36, outputs the numerical data to the memory 37, and simultaneously outputs the numeric data. DTMF receiver 32 for outputting an output status signal for notifying that there is a signal, a tri-state buffer 33 for outputting the output status signal in accordance with the enable signal supplied from the counter 36, and the tri-state buffer ( To 33) And a processor (38) for reading and analyzing numerical data stored in the memory (37) when an output status signal is supplied.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a DTMF signal receiving apparatus of a private exchange according to the present invention.

As shown in FIG. 2, the DTMF signal receiving apparatus includes a clock generator 30, a combo circuit 31, a DTMF receiver 32, a tri-state buffer 33, counters 34 and 36, and an inverter 35. , A memory 37 and a processor 38. The clock generator 30 supplies a clock signal to the combo circuit 31 and the counter 34, and the counter 34 generates a synchronization signal according to the clock signal supplied from the clock generator 30 to generate an inverter ( Output to the combo circuit 31 side through 35). The combo circuit 31 converts the digital DTMF signal supplied from the highway HW into an analog DTMF signal according to the clock signal supplied from the clock generator 30 and the synchronization signal supplied from the counter 34. Output to the receiver 32 side. The counter 36 outputs the enable signal to the DTMF receiver 32 in accordance with the address signal supplied from the processor 38 via the address bus AB and the synchronization signal S2 supplied separately, and at the same time the three states An output enable signal is output to the buffer 33 side. The DTMF receiver 32 converts the analog DTMF signal supplied from the combo circuit 31 into the corresponding numeric data and outputs the numerical data to the memory 37 through the data bus DB. Outputs a high level output state signal to the tri-state buffer 33 side.

The tri-state buffer 33 outputs the high level output state signal supplied from the DTMF receiver 32 to the processor 38 when the output enable signal is supplied from the counter 36. The processor 38 recognizes that numeric data is output from the DTMF receiver 32 to the memory 37 when the high-level output state signal is supplied from the tri-state buffer 33, and the address bus AB is output. The memory 37 is addressed to read numerical data stored in the memory 37 through a data and bus DB for analysis.

Because the circuit design is simple, the present invention improves productivity in circuit fabrication, reduces costs, and reduces the load on the system by reducing DTMF signal processing time.

Claims (1)

The counter 34 generates a synchronization signal according to the clock signal supplied from the clock generator 30, the clock supplied from the clock generator 30, and the inverter 35 from the counter 34. A combo circuit 31 for converting a digital DTMF signal from the system highway HW to an analog DTMF signal in accordance with the supplied synchronization signal, and a counter 36 for outputting an enable signal in accordance with the address signal and the synchronization signal S2. A DTMF receiver which converts the analog DTMF signal into numeric data according to the enable signal supplied from the counter 36 and outputs the numerical data to the memory 37 and outputs an output state signal for indicating that the numeric data is being output. (32), a tri-state buffer 33 for outputting the output state signal in accordance with the enable signal supplied from the counter 36, and when the output state signal is supplied from the tri-state buffer 33; DTMF signal receiving apparatus of a private exchange comprising a processor (38) for reading and analyzing numerical data stored in (37).