KR960042338A - 2's complement type serial data operator using latch circuit - Google Patents

2's complement type serial data operator using latch circuit Download PDF

Info

Publication number
KR960042338A
KR960042338A KR1019950013673A KR19950013673A KR960042338A KR 960042338 A KR960042338 A KR 960042338A KR 1019950013673 A KR1019950013673 A KR 1019950013673A KR 19950013673 A KR19950013673 A KR 19950013673A KR 960042338 A KR960042338 A KR 960042338A
Authority
KR
South Korea
Prior art keywords
input
receives
serial data
latch circuit
signal
Prior art date
Application number
KR1019950013673A
Other languages
Korean (ko)
Other versions
KR0143245B1 (en
Inventor
한규완
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950013673A priority Critical patent/KR0143245B1/en
Publication of KR960042338A publication Critical patent/KR960042338A/en
Application granted granted Critical
Publication of KR0143245B1 publication Critical patent/KR0143245B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/504—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
    • G06F7/5045—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other for multiple operands
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/544—Indexing scheme relating to group G06F7/544
    • G06F2207/5442—Absolute difference

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

본 발명은 래치 회로를 이용한 2의 보수 형태의 직렬 데이타 연산기에 관한 것으로, 입력 신호(Din)를 첫번째단(DFF1) 입력(D)으로 받고, 두번째단부터는 바로 앞단의 출력을 입력으로 받으며, 클럭 신호(CLK)를 각각 클럭 입력(CK)으로 받아,각 단에서 한 주기만큼씩 지연시켜 출력하는 지연 수단(DFF1~DFF4)과, 상기한 입력 신호(Din)를 입력(D)으로 받고, 선택_인에이블 신호(S_en)를 인에이블 입력(EN)으로 받아, 새로운 입력이 들어올 때까지 현재의 출력을 유지하는 래치 기능을수행하는 래치 회로(LAT)와, 상기 래치 회로(LAT)의 출력을 각각 1입력으로 받고, 상기 세번째 지연 수단(DFF3)과 두번째지연 수단(DFF2)의 출력(D3, D2)을 각각 0입력으로 받으며, 제1선택 신호(SEL1)와 제2선택 신호(SEL2)를 각각 선택입력(S)으로 받아, 선택 신호에 따라서 하나의 입력을 선택하여 출력하는 선택수단(MUX1, MUX2)으로 구성되었으며, 2의 보수형태의 직렬 데이타 연산시 종래의 플립플롭을 이용한 직렬 데이타 연산기에 래치 회로를 추가함으로써, 일정 비트의 부호 비트가 보장되어 있지 않는 경우에도 오차 없는 연산을 가능하게 하는 래치 회로를 이용한 2의 보수 형태의 직렬 데이타 연산기에 관한 것이다.The present invention relates to a two-complement type serial data operator using a latch circuit, which receives an input signal (Din) as the first stage (DFF1) input (D), and receives the output of the preceding stage as an input from the second stage, and receives a clock. Receives the signal CLK as the clock input CK, receives delay means DFF1 to DFF4 and outputs the delayed by one cycle at each stage, and receives the input signal Din as the input D, and selects it. A latch circuit LAT that receives the enable signal S_en as an enable input EN and performs a latch function that maintains a current output until a new input is received, and an output of the latch circuit LAT. Receive one input each, and the outputs D3 and D2 of the third delay means (DFF3) and the second delay means (DFF2) are respectively received as zero inputs, and receive the first selection signal SEL1 and the second selection signal SEL2. Each of them is received by the selection input S, and one input is selected and output according to the selection signal. It consists of the selection means (MUX1, MUX2), which adds a latch circuit to a conventional serial data operator using a flip-flop during two-complementary serial data operation, so that an error even when a sign bit of a certain bit is not guaranteed. The present invention relates to a two-complement type serial data operator using a latch circuit that enables a zero operation.

Description

래치 회로를 이용한 2의 보수 형태의 직렬 데이타 연산기2's complement type serial data operator using latch circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 실시예에 따른 래치 회로를 이용한 2의 보수 형태의 직렬 데이타 연산기의 블럭도이고, 제4도는 제3도에 도시된 직렬 데이타 연산기의 8비트 2의 보수 직렬 데이타의 연산과정을 나타낸 타이밍도이다.3 is a block diagram of a two's complement type serial data operator using a latch circuit according to an embodiment of the present invention, and FIG. 4 is an operation process of 8 bit 2's complement serial data of the serial data operator shown in FIG. Is a timing diagram.

Claims (3)

입력 신호(Din)를 첫번째단(DFF1) 입력(D)으로 받고, 두번째단부터는 바로 앞단의 출력을 입력으로 받으며, 클럭 신호(CLK)를 각각 클럭 입력(CK)으로 받아, 각 단에서 한 주기만큼씩 지연시켜 출력하는 지연수단(DFF1~DFF4)과; 상기한 입력 신호(Din)를 입력(D)으로 받고, 선택_인에이블 신호(S_en)를 인에이블 입력(EN)으로 받아, 새로운 입력이 들어올 때까지 현재의 출력을 유지하는 래치기능을 수행하는 래치 회로(LAT)와; 상기 래치 회로(LAT)의 출력을 각각 1입력으로 받고, 상기 세번째 지연 수단(DFF3)과 두번째 지연 수단(DFF2)의 출력(D3, D2)을 각각 0입력으로 받으며, 제1선택 신호(SEL1)와 제2선택 신호(SEL2)를 각각 선택 입력(S)으로 받아, 선택 신호에 따라서 하나의 입력을 선택하여 출력하는선택 수단(MUX1, MUX2)으로 이루어져 있는 것을 특징으로 하는 래치 회로를 이용한 2의 보수 형태의 직렬 데이타 연산기.Receives the input signal Din as the first stage (DFF1) input (D), receives the output of the previous stage as the input from the second stage, receives the clock signal (CLK) as the clock input (CK), respectively, one cycle at each stage. Delay means (DFF1 to DFF4) for delaying and outputting by delay; Receiving the input signal (Din) as the input (D), receives the selection_enable signal (S_en) as the enable input (EN), and performs a latch function to maintain the current output until a new input A latch circuit (LAT); Receives the output of the latch circuit LAT as one input, receives the outputs D3 and D2 of the third delay means DFF3 and DFF2 as 0 inputs, respectively, and receives the first selection signal SEL1. And selection means (MUX1, MUX2) for receiving the second selection signal SEL2 as the selection input S, respectively, and selecting and outputting one input in accordance with the selection signal. Complementary serial data operator. 제1항에 았어서, 상기한 지연 수단(DFF1~DFF4)은 디 플립플롭으로 이루어져 있는 것을 특징으로 하는 래치회로를 이용한 2의 보수 형태의 직렬 데이타 연산기.2. The two-complement type serial data operator according to claim 1, wherein the delay means (DFF1 to DFF4) are de-flip flops. 제1항에 있어서, 상기한 선택 수단(MUX1, MUX2)은 멀티풀렉서로 이루어져 있는 것을 특징으로 하는 래치회로를 이용한 2의 보수 형태의 직렬데이타 연산기.The two-complement type serial data calculator according to claim 1, wherein said selection means (MUX1, MUX2) comprise a multiplexer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950013673A 1995-05-29 1995-05-29 2's complement type serial data operating device using latch KR0143245B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950013673A KR0143245B1 (en) 1995-05-29 1995-05-29 2's complement type serial data operating device using latch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950013673A KR0143245B1 (en) 1995-05-29 1995-05-29 2's complement type serial data operating device using latch

Publications (2)

Publication Number Publication Date
KR960042338A true KR960042338A (en) 1996-12-21
KR0143245B1 KR0143245B1 (en) 1998-08-17

Family

ID=19415738

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950013673A KR0143245B1 (en) 1995-05-29 1995-05-29 2's complement type serial data operating device using latch

Country Status (1)

Country Link
KR (1) KR0143245B1 (en)

Also Published As

Publication number Publication date
KR0143245B1 (en) 1998-08-17

Similar Documents

Publication Publication Date Title
US5623223A (en) Glitchless clock switching circuit
US6507230B1 (en) Clock generator having a deskewer
JP2002182777A (en) Clock switching circuit
US4100541A (en) High speed manchester encoder
KR960042338A (en) 2's complement type serial data operator using latch circuit
JPH0865173A (en) Parallel to serial conversion circuit
KR100418017B1 (en) Data and clock recovery circuit
KR910013751A (en) NRZ / CMI (II) Code Inverter
KR100212551B1 (en) An improved apparatus for generating sync-clock of video signals
KR100366793B1 (en) Apparatus for pulse sequence generation using Shift Register
JP3072494B2 (en) Monitor circuit for channel selection status of parallel frame synchronization circuit
KR100278271B1 (en) A clock frequency divider
JPH1168861A (en) Simultaneous two-way transmission reception method and simultaneous two-way transmission reception circuit
KR100313931B1 (en) Control signal generating circuit
US7519090B2 (en) Very high speed arbitrary number of multiple signal multiplexer
JPH0738398A (en) Clock switching circuit
KR20000039962A (en) Phase locked loop circuit
JPH11112296A (en) Double edge d-flip flop circuit
JP2003223237A (en) Clock switching circuit
JPH08204524A (en) Clock phase control circuit and digital signal processing circuit using the circuit
JPH06112784A (en) Pulse generating circuit
JPS6390928A (en) Frame phase control circuit
KR980006918A (en) 50% Duty Cycle Data Generator (50% Duty Cycle Data Generator)
JPH0758732A (en) Bit buffer circuit
JPH0983499A (en) Bit phase synchronous circuit, bit phase synchronizing device and data latch timing decision circuit

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100315

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee