KR960039652A - Quantization Error Cancellation Circuit in Digital Phase-Locked Loops - Google Patents

Abstract

The present invention relates to a quantization error cancellation circuit of a digital phase locked loop. The present invention relates to a high frequency combining means for receiving a crystal oscillation signal (X-tal) as an input and generating a high frequency (HS1) to increase the accuracy of the entire system. 10) by comparing the reference input signal IN and the comparison clock signal NS1 with each other, the phase comparison means 31 for generating and outputting the phase and frequency error signal P1 of the two signals and the digital signal are filtered. Digital filtering means 32 for generating and outputting a digital signal D1 for reducing an error signal, and a clock synthesizing means 33 for generating and outputting a clock signal CKP having the same component as the reference input signal IN. And a correction means 34 for detecting a quantization error by counting an error pulse length, and outputting a clock signal from which quantization errors have been removed through timing generation and selection means, and by 1 / N division. It is composed of a divider 35 for generating and outputting the comparison clock signal NS1 to be input to the transfer means 31, eliminating quantization errors that may be present in the digital phase locked loop, and stable for a system requiring precise clock output. The present invention relates to a quantization error cancellation circuit of a digital phase locked loop which enables a stable output of a system by supplying a clock signal.

Description

Quantization Error Cancellation Circuit in Digital Phase-Locked Loops

As this is a public information case, the full text was not included.

3 is a block diagram of a quantization error cancellation circuit of a digital phase locked loop according to an embodiment of the present invention.

Claims (6)

A function to increase the accuracy of the entire system by receiving the crystal oscillation signal X-tal as an input and generating a high frequency HS1 and outputting it to the means 31, 32, 33, 34 of the digital phase locked loop 30. High frequency synthesizing means (10) for carrying out; The high frequency clock signal HS1 generated from the high frequency synthesizing means 10 and the reference input signal IN are received as inputs, and the phases of the reference input signal IN and the comparison clock signal NS1 generated therein are compared with each other. The filtered error signal P1 is filtered, and the digital signal D1 is filtered and the clock signal CKP having the same component as the reference input signal IN is generated and output. A quantization error cancellation circuit of a digital phase locked loop, characterized by comprising a digital phase locked loop for removing and outputting a quantized error with respect to an output clock (CKP). The digital phase locked loop (30) according to claim 1, wherein the digital phase locked loop (30) includes a reference input signal (IN), a comparison output signal (NS1) output from the frequency division means (35), and a high frequency clock of the high frequency synthesis means (10). A phase comparison means 31 which receives the signal HS1 as an input and compares the reference input signal IN and the comparison clock signal NS1 with each other to generate and output the phase and frequency error signal P1 of the two signals; ; Receives the phase, frequency error signal P1 and the high frequency clock signal HS1 outputted from the phase comparison means 31 as inputs, and filters the digital signal to generate and output a digital signal D1 for reducing the error signal. Digital filtration means 32; The digital signal D1 and the high frequency clock signal HS1 output from the digital filtering means 32 are received as inputs, and the two signals are synthesized to generate a clock signal CKP having the same component as the reference input signal IN. Clock synthesizing means 33 for outputting; The clock signal CKP, the high frequency clock signal HS1 and the reference input signal IN are inputted from the clock synthesizing means 33, and the quantization error is detected by counting the error pulse length to generate and select timing. Correction means (34) for outputting a clock signal from which the quantization error has been eliminated through the means; And a divider means 35 which receives the clock signal output from the correction means 34 as an input and divides 1 / N to generate and output the comparison clock signal NS1 to be input to the phase comparison means 31. A quantization error cancellation circuit of a digital phase locked loop. The high frequency clock according to claim 2, wherein the correction means (34) receives a reference input signal (IN), a high frequency clock signal (HS1), and a clock signal (CKP) output from the clock synthesizing means (33) as an input. By using the signal HS1, the pulse width from the rising edge of the reference input signal IN to the falling edge of the clock signal CKP generated from the clock synthesizing means 33 is counted and the error signal E <1: 8 Error pulse length counting means (110) for outputting &gt; The error signal E <1: 8> output from the error pulse length counting means 11 is received as an input, and the clock signal CKP output from the clock synthesizing means 33 is smaller than the reference input signal IN. Memory means (120) for generating and outputting control signals (SS, SE, SL) by judging whether the error pulse length is short or the error pulse length is long; The control signal (SS, SE, SL) output from the memory means 120 and the clock signal (CKP) output from the clock synthesizing means (33) are input, and timing is generated using the same clock (CKP) signal. A clock signal CKP2 half a cycle ahead of the reference input signal IN and a clock signal CKP1 half behind are created through the three input signals, and the three clock signals CKP, CKP1, CKP2) is a timing generation and selection means (130) for selecting and outputting a stable clock signal to a system among the digital phase locked loop quantization error elimination circuits. 4. The memory table of claim 3, wherein the memory means 120 includes a prediction table for determining whether the clock signal CKP output from the clock synthesizing means 33 precedes or falls behind the reference input signal IN. A quantization error cancellation circuit of a digital phase locked loop, characterized in that it is composed of a prediction-table ROM coded at &lt; RTI ID = 0.0 &gt; 4. The timing generating and selecting means (130) according to claim 3, wherein the timing generating and selecting means (130) receives the clock signal (CKP) output from the clock synthesizing means (33) as an input, and generates a timing signal for the same clock signal (CKP). Timing generating means (131) for generating and outputting a clock signal (CKP2) half a period ahead of the reference input signal (IN) and a clock signal (CKP1) half a cycle apart; Two clock signals CKP1 and CKP2 having a phase difference of the half period output from the timing generating means 131, a clock signal CKP output from the clock synthesizing means 33 and a control signal from the memory means 120. The selector 132 which receives the (SS, SE, SL) and selects and outputs a stable clock signal among the three clock signals CKP, CKP1 and CKP2 according to the control signals SS, SE and SL. And a quantization error cancellation circuit of a digital phase locked loop. The method of claim 5, wherein the selecting means 132 selects and outputs one clock signal among three clock signals CKP, CKP1, and CKP2 according to the input control signals SS, SE, and SL. A quantization error cancellation circuit of a digital phase locked loop, comprising: a multiplexer having a multiplexer. ※ Note: The disclosure is based on the initial application.