KR960039187A - Method of manufacturing planarized insulating film - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flattened insulating film having improved thinness and insulation without affecting semiconductor characteristics during manufacturing processes of semiconductor memory devices and non-memory devices. As the number of layers deposited due to the high integration of the semiconductor device increases, the bending of the upper layer is formed according to the given pattern of the lower part. Therefore, in order to solve this problem, a method of increasing the thickness of the insulating film has been conventionally formed. In this case, the topology As the depth increases, a problem occurs during a mask / etch process such as a contact hole, which makes it difficult to reduce the structure to a highly integrated device. Therefore, the present invention is to solve the above problems by forming a thin CVD oxide film on top of the lower layer having a topology; Forming polysilicon on the CVD oxide film; Thermally oxidizing the polysilicon; Forming a BPSG film on top of the thermal oxide film, flowing at a high temperature, and flattening by removing a predetermined portion of the BPSG film by an etch back process; It provides a planarized insulating film manufacturing method comprising the step of forming a CVD oxide film on the planarized BPSG film.

Description

Method of manufacturing planarized insulating film

As this is a public information case, the full text was not included.

2 is a cross-sectional view of an insulating film according to the planarization process of the present invention.

Claims (13)

Forming a thin CVD oxide film on top of the underlying lower layer; Forming polysilicon on the CVD oxide film; Thermally oxidizing the polysilicon; Forming a BPSG film on top of the thermal oxide film, flowing at a high temperature, and flattening by removing a predetermined portion of the BPSG film by an etch back process; And forming a CVD oxide film over the planarized BPSG film. The method of claim 1, wherein the CVD oxide film formed on the top layer of the top layer or on the planarized BPSG film is an MTO or HTO CVD oxide film. The method of claim 1 or 2, wherein the thickness of the MTO or HTO CVD oxide film formed on top of the underlying layer is 250 GPa to 350 GPa. The method of claim 3, wherein the MTO CVD oxide film is formed at a temperature of 750 ° C. to 850 ° C. in the presence of SiH ₄ and N ₂ O gas. The method of claim 3, wherein the HTO CVD oxide film is formed at a temperature of 850 ° C. to 950 ° C. in the presence of SiH ₂ Cl ₂ and N ₂ O gas. The method of claim 1, wherein the thickness of the polysilicon on the CVD oxide film is about 100 microns. The method of claim 1, wherein the polysilicon film is formed by pyrolysing SiH ₄ gas at a temperature range of 620 ± 20 ° C. by LP-CVD. The method of claim 1, wherein the polysilicon film is thermally oxidized at a temperature of 700 to 800 ° C. in the presence of O ₂ gas or a mixed gas of O ₂ and H ₂ . The method of claim 8, wherein the thermally oxidized polysilicon film has a thickness of 150 kPa to 200 kPa. The method of claim 1, wherein a BPSG film is formed on the thermally oxidized polysilicon film at a temperature of 800 ° C to 900 ° C. The method of claim 10, wherein the BPSG film has a thickness of 4,000 kPa to 5,000 kPa. The method of claim 1, wherein the BPSG film is partially removed from the region of 2,000 kPa to 3,000 kPa by an anisotropic reactive ion etchback process. The method of claim 1 or 2, wherein the MTO or HTO CVD oxide film formed on the planarized BPSG film has a thickness of 450 kW to 550 kW. ※ Note: The disclosure is based on the initial application.