KR960038993A - Bit line precharge circuit, equalization circuit and arrangement method - Google Patents

Bit line precharge circuit, equalization circuit and arrangement method Download PDF

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Publication number
KR960038993A
KR960038993A KR1019950010164A KR19950010164A KR960038993A KR 960038993 A KR960038993 A KR 960038993A KR 1019950010164 A KR1019950010164 A KR 1019950010164A KR 19950010164 A KR19950010164 A KR 19950010164A KR 960038993 A KR960038993 A KR 960038993A
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KR
South Korea
Prior art keywords
circuit
region
equalization
precharge
equalization circuit
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Application number
KR1019950010164A
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Korean (ko)
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KR0158113B1 (en
Inventor
정우표
전준영
Original Assignee
김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950010164A priority Critical patent/KR0158113B1/en
Publication of KR960038993A publication Critical patent/KR960038993A/en
Application granted granted Critical
Publication of KR0158113B1 publication Critical patent/KR0158113B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits

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  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

1. 청구범위에 기재된 발명이 속하는 기술 분야 :1. The technical field to which the invention described in the claims belongs:

본 발명은 비트라인 프라차아지회로와 등화회로 및 그 배치방법에 관한 것이다.The present invention relates to a bit line pracharge circuit, an equalization circuit and a method of arranging the same.

2. 발명이 해결하려고 하는 기술적 과제 :2. The technical problem to be solved by the invention:

센스앰프회로에 단위메모리셀블럭이 공통으로 접속되는 종래의 프리차아지회로 및 등화회로에서는 분리게이트로 구분되는 비트라인의 영역에 따라 프라차아지 및 등화특성이 다르므로서 엑세스동작이 느리고 오동작이 발생하는 등의 문제점이 있었다.In conventional precharge circuits and equalization circuits in which unit memory cell blocks are commonly connected to the sense amplifier circuits, the access operation is slow and malfunctions are different due to the difference of the Pracharge and equalization characteristics depending on the area of the bit line divided by the separation gate. There was a problem such as occurring.

3. 발명의 해결방법의 요지 :3. Summary of the solution of the invention:

본 발명에서는 분리게이트로 구분되는 각 영역마다 프리차아지회로 및 등화회로를 구비하므로서 프리차아지 및 등화특성을 개선하였다.In the present invention, the precharge circuit and the equalization circuit are improved by providing a precharge circuit and an equalization circuit for each region divided by the separation gate.

4. 발명의 중요한 용도 :4. Important uses of the invention:

각 영역마다 독립적으로 프리차아지 및 등화되는 회로를 구비하므로서 프리차아지 및 등화속도가 빨라졌고 오동작 없는 안정된 반도체 메모리장치가 구현된다. 이러한 회로는 저전원전압일 때 더욱 탁월한 효과를 발휘하게 된다.Since each region has a precharge and equalization circuit independently, the precharge and equalization speeds are increased and a stable semiconductor memory device without malfunction is realized. This circuit is more effective at low power supply voltage.

Description

비트라인 프리차아지회로와 등화회로 및 그 배치방법Bit line precharge circuit, equalization circuit and arrangement method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 의한 프리차아지회로 및 등화회로의 제1배치도.3 is a first layout diagram of a precharge circuit and an equalization circuit according to the present invention.

Claims (5)

제1메모리셀이 형성된 제1영역과 제2메모리셀이 형성된 제2영역이 한쌍의 비트라인 및 센스앰프회로를 공유하고 상기 센스앰프회로는 상기 제1영역과 제2영역사이의 제3영역에 형성되고 상기 각각의 영역은 제1분리게이트와 제2분리게이트에 의해 분리되는 반도체 메모리장치의 프리차아지회로 및 등화회로의 배치방법에 있어서, 상기 제1영역과 제2영역 및 제3영역에 각각 하나씩의 프리차아지회로 및 등화회로를 구비함을 특징으로하는 반도체 메모리장치의 프리차아지회로 및 등화회로의 배치방법.The first region in which the first memory cell is formed and the second region in which the second memory cell are formed share a pair of bit lines and a sense amplifier circuit, and the sense amplifier circuit is disposed in a third region between the first region and the second region. And a precharge circuit and an equalization circuit of the semiconductor memory device, wherein each region is formed by a first separation gate and a second separation gate, wherein each region is formed in the first region, the second region, and the third region. A precharge circuit and an equalization circuit arrangement method of a semiconductor memory device, characterized by comprising one precharge circuit and an equalization circuit. 제1항에 있어서, 상기 제2영역이 등화회로로 구성됨을 특징으로하는 반도체 메모리장치의 프리차아지회로 및 등화회로의 배치방법.2. The method as claimed in claim 1, wherein said second region comprises an equalization circuit. 제1항에 있어서, 상기 제1영역 및 제2영역이 등화회로로 구성됨을 특징으로하는 반도체 메모리장치의 프리차아지회로 및 등화회로의 배치방법.The method of claim 1, wherein the first region and the second region comprise an equalization circuit. 제1항에 있어서, 상기 제1영역 과 제3영역이 프리차아지회로 구성되고, 상기 제2영역이 등화회로로 구성됨을 특징으로하는 반도체 메모리장치의 프리차아지회로 및 등화회로의 배치방법.2. The method of claim 1, wherein the first region and the third region comprise a precharge circuit and the second region comprises an equalization circuit. 다수개의 비트라인쌍을 구비하고 한쌍의 비트라인사이에 적어도 하나의 센스앰회로와 적어도 하나의 프리차아지회로 및 등화회로를 구비하고 메모리블록을 분리하여 사용하는 분리게이트를 가지는 반도체 메모리장치에 있어서, 상기 분리게이트로 구분되는 영역에 적어도 하나씩의 프리차아지회로 또는 적어도 하나씩의 등화회로를 구비함을 특징으로 하는 반도체 메모리장치.A semiconductor memory device comprising a plurality of bit line pairs, at least one sense amplifier circuit, at least one precharge circuit, and an equalization circuit between a pair of bit lines, and having a separation gate for separating and using a memory block. And at least one precharge circuit or at least one equalization circuit in a region divided by the separation gate. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019950010164A 1995-04-27 1995-04-27 Bit line precharge circuit and equalizing circuit KR0158113B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950010164A KR0158113B1 (en) 1995-04-27 1995-04-27 Bit line precharge circuit and equalizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950010164A KR0158113B1 (en) 1995-04-27 1995-04-27 Bit line precharge circuit and equalizing circuit

Publications (2)

Publication Number Publication Date
KR960038993A true KR960038993A (en) 1996-11-21
KR0158113B1 KR0158113B1 (en) 1999-02-01

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Publication number Priority date Publication date Assignee Title
KR100871958B1 (en) * 2002-07-18 2008-12-08 주식회사 하이닉스반도체 Semiconductor memory device

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