KR960036776A - Convolutional Encoder and Decoder with Parallel Structure - Google Patents

Convolutional Encoder and Decoder with Parallel Structure Download PDF

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Publication number
KR960036776A
KR960036776A KR1019950005804A KR19950005804A KR960036776A KR 960036776 A KR960036776 A KR 960036776A KR 1019950005804 A KR1019950005804 A KR 1019950005804A KR 19950005804 A KR19950005804 A KR 19950005804A KR 960036776 A KR960036776 A KR 960036776A
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South Korea
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encoder
decoder
parallel
convolutional
systemic
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KR1019950005804A
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Korean (ko)
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KR0153674B1 (en
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박영록
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배순훈
대우전자 주식회사
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
    • H03M13/235—Encoding of convolutional codes, e.g. methods or arrangements for parallel or block-wise encoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/612—Aspects specific to channel or signal-to-noise ratio estimation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Error Detection And Correction (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

본 발명에 의한 병렬 구조를 갖는 길쌈 부호기 및 복호기는 기존의 길쌈 부호기/복호기에 계통적 길쌈 부호기 및 복호기를 병렬로 연결하여 구현한 것으로서, 두개의 계통적, 비계통적 길쌈 코드를 채널 예측기의 신호대 잡음비 추정 결과에 따라 신호대 잡음비가 낮은 경우는 계통적 길쌈 코드를 선택하게 하고, 신호대 잡음비가 높을 경우는 추출된 비계통적 길쌈 코드을 선택하게 함으로써 채널의 변화가 심한 시스템에서도 높은 전송률 및 좋은수신을 할 수 있게 한 것이다.A convolutional encoder and decoder having a parallel structure according to the present invention is implemented by connecting a systematic convolutional encoder and a decoder to a conventional convolutional encoder / decoder in parallel. Therefore, when the signal-to-noise ratio is low, the systematic convolutional code is selected, and when the signal-to-noise ratio is high, the extracted non-systemic convolutional code is selected so that high transmission rate and good reception can be achieved even in a system with a large channel change.

Description

병렬 구조를 갖는 길쌈 부호기 및 복호기Convolutional Encoder and Decoder with Parallel Structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는(가)는 본 발명의 병렬 구조를 갖는 길쌈 부호기를 도시한 개략적인 블럭선도, (나)는 본 발명의 병렬 구조를 갖는 길쌈 복호기를 도시한 개략적인 블럭선도이다.2 is a schematic block diagram showing a convolutional encoder having a parallel structure of the present invention, and (b) is a schematic block diagram showing a convolutional decoder having a parallel structure of the present invention.

Claims (2)

디지탈 통신 시스템에서 여러 요인에 의하여 필연적으로 발생하는 에러를 검출하고 정정하기 위한 부호기와 상기 부호기에서 전송된 데이타를 수신하여 채널에 의해 발생한 데이타 오류를 바로잡는 복호기에 있어서, 상기 부호기는 정보를 포함하지 않는 부호어를 전송하는 비계통적 길쌈 부호기(10)와, 상기 비계통적 길쌈 부호기(10)에 전송된 부호어중 일부를 추출하여 전송하는 추출부(20)와, 상기 비계통적 길쌈 부호기(10)에 병렬로 연결되어 정보와 패리티를 포함하는 부호어를 전송하는 계통적 길삼 부호기(30) 및, 상기 각각의 신호를 다중화하여 채널을 통해 전송하는 멀티플랙서(40)로 구성되고; 상기 복호기는 상기 부호기에서 전송된 신호를 원신호를 복원하는 디멀티플랙서(50)와, 상기 추출부(20)에서 추출하여 보내지 않은 부분을 복원하여 전송하는 이레이져 삽입부(60), 상기 이레이져 삽입부(60)에서 전송된 정보를 전송하는 비계통적 길쌈 복호기(70)와 정보를 포함하는 계통적 길쌈 복호기(80)가 병렬로 연결되어 각각의 데이타를 병렬 전송하는 한편 채널 예측기(90)에 의해 추정한 신호대 잡음비에 따라 멀티플랙서(100)에서 하나의 신호를 선택하게 하는 구조로된 것을 특징으로 하는 병렬 구조를 갖는 길쌈 부호기 및 복호기.In a digital communication system, an encoder for detecting and correcting an error inevitably caused by various factors and a decoder for receiving data transmitted from the encoder and correcting a data error caused by a channel, wherein the encoder does not include information. A non-systemic convolutional encoder 10 which transmits a codeword which is not included, an extractor 20 which extracts and transmits a portion of codewords transmitted to the non-systemic convolutional encoder 10, and the non-systemic convolutional encoder 10 A parallel path coder 30 connected in parallel to transmit codewords including information and parity, and a multiplexer 40 for multiplexing each signal and transmitting the codeword; The decoder includes a demultiplexer 50 for restoring the original signal from the encoder, an erasure inserter 60 for restoring a portion not extracted and extracted from the extractor 20, and The non-systematic convolutional decoder 70 for transmitting the information transmitted from the erasure inserter 60 and the systematic convolutional decoder 80 including the information are connected in parallel to transmit the respective data in parallel while the channel predictor 90 A convolutional encoder and decoder having a parallel structure, characterized in that the multiplexer (100) to select one signal according to the signal-to-noise ratio estimated by the. 제1항에 있어서, 상기 부호기는, 비계통적 길쌈 부호기(10)와 계통적 길쌈 부호기(30)가 서로 병렬로 연결되어 추출한 비계통적 길쌈 코드와 계통적 길쌈 코드를 서로 병렬로 전송하는 것을 특징으로 하는 병렬 구조를 갖는 길쌈 부호기 및 복호기.According to claim 1, wherein the encoder, the non-systemic convolutional coder 10 and the systematic convolutional coder 30 is connected in parallel to each other in parallel parallel transmission characterized in that the extracted non-systemic convolutional code and systematic convolutional code Weaving encoder and decoder with structure. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950005804A 1995-03-20 1995-03-20 A convolutional encoder and decoder having a parallel structure KR0153674B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950005804A KR0153674B1 (en) 1995-03-20 1995-03-20 A convolutional encoder and decoder having a parallel structure

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KR960036776A true KR960036776A (en) 1996-10-28
KR0153674B1 KR0153674B1 (en) 1998-11-16

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