KR960035922A - Method for manufacturing field effect transistor - Google Patents

Method for manufacturing field effect transistor Download PDF

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Publication number
KR960035922A
KR960035922A KR1019950005972A KR19950005972A KR960035922A KR 960035922 A KR960035922 A KR 960035922A KR 1019950005972 A KR1019950005972 A KR 1019950005972A KR 19950005972 A KR19950005972 A KR 19950005972A KR 960035922 A KR960035922 A KR 960035922A
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KR
South Korea
Prior art keywords
insulating layer
source
drain region
semiconductor substrate
effect transistor
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KR1019950005972A
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Korean (ko)
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KR0140785B1 (en
Inventor
장경식
이윤종
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019950005972A priority Critical patent/KR0140785B1/en
Publication of KR960035922A publication Critical patent/KR960035922A/en
Application granted granted Critical
Publication of KR0140785B1 publication Critical patent/KR0140785B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 기본 반도체 소자 중 하나로서, 메모리 소자나 디지탈회로와 같은 곳에 필수적으로 사용되는 메사형 구조의 전계효과 트랜지스터 제조방법에 관한 것으로, 이는 게이트 전극의 마진을 감소시키고도 고집적시의 차단특성 저하를 방지할 수 있고, 셀 면적을 감소시킬 수 있으며, 아울러 게이트 전극이 형성되는 채널을 둘러싸도록 형성되어 있기 때문에 기판전압의 변화와 큰 영향을 받지 않아 소자의 신뢰성을 향상시킬 수 있는 특유의 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field effect transistor having a mesa structure, which is essentially used in a memory device or a digital circuit, such as a semiconductor device. Can be prevented, the cell area can be reduced, and the gate electrode is formed so as to surround the channel where the gate electrode is formed. have.

Description

전계효과 트랜지스터 제조방법Method for manufacturing field effect transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2C도는 본 발명의 일실시예에 따른 전계효과 트랜지스터의 형성 공정 단면도, 제3도는 제 2C도의 사시도.2A to 2C are cross-sectional views of a process for forming a field effect transistor according to an embodiment of the present invention, and FIG. 3 is a perspective view of FIG. 2C.

Claims (5)

전계효과 트랜지스터 제조방법에 있어서, 소스/드레인 영역이 형성될 부위를 제외한 반도체 기판상의 나머지 부위를 일정 깊이를 식각하는 단계; 게이트 절연층과 게이트 전극을 형성하되, 상기 게이트 절연층은 상기 반도체기판의 표면에 형성하는 단계; 및 상기 소스/드레인 영역이 형성될 부위에 불순물을 이온주입하는 단계를 포함하는 것을 특징으로 하는 전계효과 트랜지스터 제조방법.A method for manufacturing a field effect transistor, comprising: etching a predetermined depth of a remaining portion of a semiconductor substrate except for a portion where a source / drain region is to be formed; Forming a gate insulating layer and a gate electrode, the gate insulating layer being formed on a surface of the semiconductor substrate; And implanting impurities into a portion where the source / drain region is to be formed. 전계효과 트랜지스터 제조방법에 있어서, 소스/드레인 영역이 형성될 부위를 제외한 반도체 기판상의 나머지 부위를 일정 깊이로 삭각하는 단계; 상기 반도체기판의 일정 깊이가 제거된 부위에 절연층을 형성하되, 상기 절연층은 상부 표면이 상기 소스/드레인 영역이 형성될 부위의 상부 표면보다 밑에 위치하도록 형성하는 단계; 게이트 절연층과 게이트 전극을 차례로 형성하되, 상기 게이트 절연층은 상기 노출된 절연층 및 반도체기판의 표면에 형성하는 단계; 및 상기 소스/드레인 영역이 형성될 부위에 불순물을 이온주입하는 단계를 포함하는 것을 특징으로 하는 전계효과 트랜지스터 제조방법.CLAIMS What is claimed is: 1. A method for manufacturing a field effect transistor, comprising: cutting a remaining portion on a semiconductor substrate to a predetermined depth except for a portion where a source / drain region is to be formed; Forming an insulating layer on a portion from which a predetermined depth of the semiconductor substrate is removed, wherein the insulating layer is formed such that an upper surface is positioned below an upper surface of a portion where the source / drain region is to be formed; Forming a gate insulating layer and a gate electrode in sequence, wherein the gate insulating layer is formed on surfaces of the exposed insulating layer and the semiconductor substrate; And implanting impurities into a portion where the source / drain region is to be formed. 제2항에 있어서, 상기 반도체기판의 일정 깊이가 제거된 부위에 절연층을 형성하되, 상기 절연층은 상부 표면이 상기 소스/드레인 영역이 형성될 부위의 상부 표면보다 밑에 위치하도록 형성하는 단계는, 전체구조 상부에 절연층을 형성하는 단계; 및 상기 소스/드레인 영역이 형성된 부위의 일부 두께가 노출될 때까지 에치백(Etchback)하는 단계를 포함하는 것을 특징으로 하는 전계효과 트랜지스터 제조방법.The method of claim 2, wherein an insulating layer is formed on a portion from which a predetermined depth of the semiconductor substrate is removed, and the insulating layer is formed such that an upper surface is located below an upper surface of a portion where the source / drain region is to be formed. Forming an insulating layer on the entire structure; And etching back until a part thickness of the portion where the source / drain region is formed is exposed. 제2항 또는 제3항에 있어서, 상기 절연층은, 붕소와 인으로 구성된 그룹중에서 선택된 물질을 포함하는 실리케이트 유리(Silicate Glass)층이나 산화층인 것을 특징으로 하는 전계효과 트랜지스터 제조방법.The method of claim 2 or 3, wherein the insulating layer is a silicate glass layer or an oxide layer containing a material selected from the group consisting of boron and phosphorus. 제 4항에 있어서, 실리게이트 유리층은, BPSG, BSG, PSG로 구성된 그룹 중에서 선택된 물질로 이루어지는 것을 특징으로 하는 전계효과 트랜지스터 제조방법.The method of claim 4, wherein the silicide glass layer is formed of a material selected from the group consisting of BPSG, BSG, and PSG. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950005972A 1995-03-21 1995-03-21 Fabrication method of mosfet KR0140785B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950005972A KR0140785B1 (en) 1995-03-21 1995-03-21 Fabrication method of mosfet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950005972A KR0140785B1 (en) 1995-03-21 1995-03-21 Fabrication method of mosfet

Publications (2)

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KR960035922A true KR960035922A (en) 1996-10-28
KR0140785B1 KR0140785B1 (en) 1998-07-15

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KR1019950005972A KR0140785B1 (en) 1995-03-21 1995-03-21 Fabrication method of mosfet

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KR0140785B1 (en) 1998-07-15

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