KR960032754A - Nonvolatile Memory Device and Manufacturing Method - Google Patents

Nonvolatile Memory Device and Manufacturing Method Download PDF

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KR960032754A
KR960032754A KR1019950003022A KR19950003022A KR960032754A KR 960032754 A KR960032754 A KR 960032754A KR 1019950003022 A KR1019950003022 A KR 1019950003022A KR 19950003022 A KR19950003022 A KR 19950003022A KR 960032754 A KR960032754 A KR 960032754A
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field oxide
conductive layer
forming
layer
floating gate
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최용배
김건수
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

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Abstract

불휘발성 메모리장치 및 그 제조방법에 대해 기재되어 있다. 이는 반도체기판에 일방향으로 길게 형성된 제1 및 제2필드산화막, 상기 제1 및 제2필드산화막 사이의 반도체기판 상에 형성된 제1절연막, 상기 제1필드산화막, 제1절연막 및 제2필드산화막 상에 걸쳐 형성된 사각형의 플로우팅 게이트, 그 측벽이 상기 플로우팅 게이트의 일측벽과 수직선상에 위치하고, 상기 제1 및 제2필드 산화막의 길이 방향을 따라 길게, 상기 제1 및 제2필드산화막에 형성된 홈 및 상기 홈의 측벽과 상기 플로우팅 게이트의 일측벽에 걸쳐 형성된 스페이서를 포함하는 것을 특징으로 한다. 따라서 소자에 인가되는 전압의 크기를 줄일 수 있으므로, 반도체 메모리장치의 신뢰도를 향상시킨다.A nonvolatile memory device and a method of manufacturing the same are described. The first and second field oxide films formed on the semiconductor substrate in one direction, the first insulating film formed on the semiconductor substrate between the first and second field oxide films, the first field oxide film, the first insulating film, and the second field oxide film. A rectangular floating gate formed over the sidewall, the sidewall of which is disposed on a vertical line with one side wall of the floating gate, and formed along the longitudinal direction of the first and second field oxide films, And a spacer formed over the sidewall of the groove and one side wall of the floating gate. Therefore, the magnitude of the voltage applied to the device can be reduced, thereby improving the reliability of the semiconductor memory device.

Description

불휘발성 메모리장치 및 그 제조방법Nonvolatile Memory Device and Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3A도 및 제3B도는 본 발명의 일 실시예에 의해 제조된 플레시 EEPROM의 단면도들로서, 제3A도는 상기 제1A도 및 제1B도의 AA′선을 잘라 본 것이고, 제3B도는 상기 제1A도 및 제1B도의 BB′선을 잘라 본 것이다.3A and 3B are cross-sectional views of a flash EEPROM manufactured according to an embodiment of the present invention. The BB 'line of FIG. 1B is cut out.

Claims (13)

반도체 기판에 일방향으로 길게 형성된 제1 및 제2필드산화막; 상기 제1 및 제2필드 산화막 사이의 반도체 기판 상에 형성 제1절연막; 상기 제1필드산화막, 제1절연막 및 제2필드산화막 상에 걸쳐 형성 사각형의 플로우팅 게이트; 그 측벽이 상기 플로우팅 게이트의 일측벽과 수직선상에 위치하고, 상기 제1 및 제2필드산화막의 길이 방향을 따라 길게, 상기 제1 및 제2필드산화막에 형성된 홈; 및 상기 홈의 측벽과 상기 플로우팅 게이트의 일측벽에 걸쳐 형성된 스페이서를 포함하는 것을 특징으로 하는 불휘발성 메모리장치.First and second field oxide films elongated in one direction on the semiconductor substrate; A first insulating film formed on the semiconductor substrate between the first and second field oxide films; A rectangular floating gate formed over the first field oxide film, the first insulating film, and the second field oxide film; Grooves formed on the first and second field oxide films, the sidewalls of which are disposed on a vertical line with one side wall of the floating gate and extending along the length direction of the first and second field oxide films; And a spacer formed over the side wall of the groove and one side wall of the floating gate. 제1항에 있어서, 상기 스페이서는 상기 플로우팅 게이트를 구성하는 물질과 동일한 성질의 물질로 구성되어 있는 것을 특징으로 하는 불휘발성 메모리장치.The nonvolatile memory device of claim 1, wherein the spacer is made of a material having the same property as that of the material forming the floating gate. 제2항에 있어서, 상기 플로우팅 게이트 및 스페이서를 구성하는 물질은 불순물이 도우프된 다결정실리콘인 것을 특징으로 하는 불휘발성 메모리장치.The nonvolatile memory device of claim 2, wherein the material constituting the floating gate and the spacer is polycrystalline silicon doped with impurities. 제1항에 있어서, 상기 스페이서 및 플로우팅 게이트의 각 최상부 표면에 형성된 제2절연막을 더 포함하는 것을 특징으로 하는 불휘발성 메모리장치.The nonvolatile memory device of claim 1, further comprising a second insulating layer formed on uppermost surfaces of the spacers and the floating gate. 반도체기판에 일방향으로 길게 제1 및 제2필드산화막을 형성하는 제1공정; 상기 제1 및 제2필드 산화막 사이로 표면으로 노출된 상기 반도체기판 상에 제1절연막을 형성하는 제2공정; 결과물 전면에 제1도전층을 형성하는 제3공정; 상기 제1도전층 상에 식각방지층을 형성하는 제4공정; 일방향으로 긴 막대모양으로 형성된 감광막패턴을 식각마스크로 하여 상기 제1도전층 및 식각방지층을 패터닝하는 제5공정; 상기 감광막패턴을 식각마스크로 하여 필드산화막들을 식각함으로써 상기 필드산화막들에 홈을 형성하는 제6공정; 결과물 상에 제2도전층을 형성하는 제7공정; 상기 제2도전층을 식각대상물로 한 이방성식각 공정을 행하여, 긴 막대모앙으로 패터닝된 상기 제1도전층의 측벽 및 상기 홈의 측벽에 걸쳐 스페이서를 형성하는 제8공정; 상기 식각방지층을 제거하는 제9공정; 결과물 전면에 제2절연막을 형성하는 제10공정; 상기 제2절연막 상에 제2도전층을 형성하는 제11공정; 및 상기 제3도전층, 제2절연막 및 제1도전층을 상기 일방향에 대해 수직방향으로 긴 막대모양으로 패터닝하는 제12공정을 포함하는 것을 특징으로 하는 불휘발성 메모리장치의 제조방법.Forming a first and second field oxide film on the semiconductor substrate in one direction; A second step of forming a first insulating film on the semiconductor substrate exposed to the surface between the first and second field oxide films; A third step of forming a first conductive layer on the entire surface of the resultant product; A fourth step of forming an etch stop layer on the first conductive layer; A fifth process of patterning the first conductive layer and the etch stop layer by using the photoresist pattern formed in a long bar shape in one direction as an etching mask; A sixth step of forming grooves in the field oxide films by etching the field oxide films using the photoresist pattern as an etching mask; A seventh step of forming a second conductive layer on the resultant; An eighth step of performing an anisotropic etching process using the second conductive layer as an etching target to form a spacer over the sidewall of the first conductive layer and the sidewall of the groove patterned into a long rod; A ninth step of removing the etch stop layer; A tenth step of forming a second insulating film on the entire surface of the resultant product; An eleventh step of forming a second conductive layer on the second insulating film; And a twelfth step of patterning the third conductive layer, the second insulating layer, and the first conductive layer into long rods in a direction perpendicular to the one direction. 제5항에 있어서, 상기 제6공정 이후에 상기 반도체기판에, 상기 반도체기판의 도전형과 동일한 도전형의 불순물이온을 주입하는 공정을 더 포함하는 것을 특징으로 하는 불휘발성 메모리장치의 제조방법.The method of claim 5, further comprising, after the sixth step, injecting impurity ions having the same conductivity type as those of the semiconductor substrate into the semiconductor substrate. 제5항에 있어서, 상기 식각방지층은, 소정의 식각에 대해 상기 제1도전층을 구성하는 물질과는 다른 식각율을 갖는 물질로 구성되는 것을 사용하는 특징으로 하는 불휘발성 메모리장치의 제조방법.The method of claim 5, wherein the etch stop layer is formed of a material having an etching rate different from that of the material constituting the first conductive layer for a predetermined etching. 제7항에 있어서, 상기 식각방지층은, 산화막으로 구성되는 것을 특징으로 하는 불휘발성 메모리장치의 제조방법.The method of claim 7, wherein the etch stop layer is formed of an oxide film. 제8항에 있어서, 상기 산화막은 화학기상증착법으로 형성되는 것을 특징으로 하는 불휘발성 메모리장치의 제조방법.The method of claim 8, wherein the oxide layer is formed by chemical vapor deposition. 제5항에 있어서, 상기 제2도전층은 상기 제1도전층을 구성하는 물질과 동일한 성질의 물질로 구성되는 것을 특징으로 하는 불휘발성 메모리장치의 제조방법.The method of claim 5, wherein the second conductive layer is formed of a material having the same properties as a material constituting the first conductive layer. 제7항 및 제10항 중 어느 한 항에 있어서, 상기 제1, 제2 및 제3도전층은 불순물이 도우프된 다결정실리콘으로 구성되는 것을 특징으로 하는 불휘발성 메모리장치의 제조방법.The method of claim 7, wherein the first, second, and third conductive layers are made of polycrystalline silicon doped with impurities. 제5항에 있어서, 상기 제6공정 시, 필드산화막은 건식식각에 의해, 500A -3,000A정도의 깊이로 식각되는 것을 특징으로 하는 불휘발성 메모리장치의 제조방법.The method of claim 5, wherein, in the sixth step, the field oxide film is etched to a depth of about 500A to 3,000A by dry etching. 제5항에 있어서, 상기 제1절연막은 산화막으로 형성되고, 상기 제2절연막은 산화막/질화막/산화막으로 형성되는 것을 특징으로 하는 불휘발성 메모리장치의 제조방법.6. The method of claim 5, wherein the first insulating layer is formed of an oxide film, and the second insulating layer is formed of an oxide film / nitride film / oxide film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950003022A 1995-02-17 1995-02-17 Non-volatile memory device & method for making the same KR0161391B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020044261A (en) * 2000-12-05 2002-06-15 박종섭 Method of manufacturing a flash memory cell
KR100470987B1 (en) * 1997-08-28 2005-07-05 삼성전자주식회사 Low voltage nonvolatile memory device and manufacturing method thereof

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990004416A (en) * 1997-06-27 1999-01-15 김영환 Flash cell manufacturing method of semiconductor device
KR20020095690A (en) * 2001-06-15 2002-12-28 주식회사 하이닉스반도체 Method of manufacturing flash memory device
US6911370B2 (en) * 2002-05-24 2005-06-28 Hynix Semiconductor, Inc. Flash memory device having poly spacers

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100470987B1 (en) * 1997-08-28 2005-07-05 삼성전자주식회사 Low voltage nonvolatile memory device and manufacturing method thereof
KR20020044261A (en) * 2000-12-05 2002-06-15 박종섭 Method of manufacturing a flash memory cell

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