KR960030445A - Thin film transistor manufacturing method and its structure - Google Patents

Thin film transistor manufacturing method and its structure Download PDF

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Publication number
KR960030445A
KR960030445A KR1019950000851A KR19950000851A KR960030445A KR 960030445 A KR960030445 A KR 960030445A KR 1019950000851 A KR1019950000851 A KR 1019950000851A KR 19950000851 A KR19950000851 A KR 19950000851A KR 960030445 A KR960030445 A KR 960030445A
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South Korea
Prior art keywords
conductive layer
gate
forming
gate insulating
thin film
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KR1019950000851A
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Korean (ko)
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KR0151020B1 (en
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박용
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

스태틱 랜덤 억세스 메모리(SRAM) 셀의 박막 트랜지스터 제조방법 및 그 구조에 관하여 개시한다. 본 발명은 반도체 기판상에 게이트용 제1도전층을 형성하는 단계와, 상기게이트용 제1도전층을 패터닝하여 게이트를 형성하는 단계와, 상기 게이트가 형성된 기판의 전면에 게이트 절연막을 형성하는 단계와, 상기 게이트 절연막상에 바디용 제2도전층을 형성하는 단계와, 상기 바디용 제2도전층 및 게이트 절연막을 식각하여, 상기 게이트 절연막상의 일부에 콘택홀을 형성하는 단계와, 상기 콘택홀이 형성된 결과물상에 바디용 제3도전층을 형성하는 단계와, 상기 바디용 제3도전층의 전면에 채널이온 주입을 실시하는 단계를 포함한다. 본 발명에 의하면 게이트 절연막의 두께를 얇게 할 수 있어서 박막 트랜지스터의 온상태에서 전류구동능력을 향상시켜 셀의 안정도, 소프트에러 내성의 강화, 노이즈(noise) 면역성, 및 저(low) 스탠드-바이전류등의 동작 특성을 개선 할 수 있다.A method and a structure of a thin film transistor of a static random access memory (SRAM) cell are disclosed. The present invention provides a method of fabricating a semiconductor substrate, the method comprising: forming a gate first conductive layer on a semiconductor substrate; patterning the gate first conductive layer; forming a gate; Forming a second conductive layer for a body on the gate insulating film, etching the second conductive layer for the body and a gate insulating film to form a contact hole on a portion of the gate insulating film, and forming the contact hole. And forming a third conductive layer for a body on the formed product, and performing channel ion implantation on the entire surface of the third conductive layer for the body. According to the present invention, the thickness of the gate insulating film can be reduced, thereby improving the current driving capability in the on state of the thin film transistor, thereby improving cell stability, enhancing soft error tolerance, noise immunity, and low stand-by current. It can improve the operation characteristics.

Description

박막 트랜지스터(TFT) 제조방법 및 그 구조Thin film transistor manufacturing method and its structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 박막 트랜지스터의 단면도이다.2 is a cross-sectional view of a thin film transistor according to the present invention.

Claims (6)

반도체 기판상에 게이트용 제1도전층을 형성하는 단계; 상기 게이트용 제1도전층을 패터닝하여 게이트를 형성하는 단계; 상기 게이트가 형성된 기판의 전면에 게이트 절연막을 형성하는 단계; 상기 게이트 절연막상에 바디용 제2도전층을 형성하는 단계; 상기 바디용 제2도전층 및 게이트 절연막을 식각하여, 상기 게이트 절연막 상의 일보에 콘택홀을 형성하는 단계; 상기 콘택홀이 형성된 결과물상에 바디용 제3도전층을 형성하는 단계; 및 상기 바디용 제3도전층의 전면에 채널이온 주입을 실시하는 단계를 포함하는 것을 특징으로 하는 박막 트랜지스터의 제조방법.Forming a first conductive layer for a gate on the semiconductor substrate; Patterning the gate first conductive layer to form a gate; Forming a gate insulating film on an entire surface of the substrate on which the gate is formed; Forming a second conductive layer for a body on the gate insulating film; Etching the second conductive layer and the gate insulating layer for the body to form a contact hole in the daily report on the gate insulating layer; Forming a third conductive layer for a body on the resultant product in which the contact hole is formed; And injecting channel ions into the entire surface of the third conductive layer for the body. 제1항에 있어서, 상기 바디용 제2도전층을 형성하는 단계전에, 게이트 절연막을 손상시키지 않는 식각액을 사용하여 상기 제1도전층이 형성된 기판을 세척하는 단계가 더 포함되는 것을 특징으로 하는 박막 트랜지스터의 제조방법.The thin film of claim 1, further comprising, before the forming of the second conductive layer for the body, cleaning the substrate on which the first conductive layer is formed using an etchant that does not damage the gate insulating layer. Method for manufacturing a transistor. 제1항에 있어서, 상기 바디용 제3도전층을 형성하는 단계후에, 상기 바디용 제3도전층을 산화시키는 단계를 더 포함하는 것을 특징으로 하는 박막 트랜지스터의 제조방법.The method of claim 1, further comprising, after the forming of the third conductive layer for the body, oxidizing the third conductive layer for the body. 제1항에 있어서, 상기 제1도전층, 제2도전층 및 제3도전층을 구성하는 물질로 다결정실리콘 또느 비정질실리콘을 사용하는 것을 특징으로 하는 박막 트랜지스터의 제조방법.The method of claim 1, wherein polycrystalline silicon or amorphous silicon is used as a material constituting the first conductive layer, the second conductive layer, and the third conductive layer. 반도체 기판상에 형성된 박막 트랜지스터의 게이트; 상기 게이트 및 기판의 전면에 형성되고, 상기 게이트상의 일부에 콘택홀을 갖는 게이트 절연막; 상기 게이트 절연막상에 형성된 바디용 제2도전층; 및 상기 콘택홀이 형성된 바디용 제2도전층의 전면에 형성된 바디용 제3도전층으로 이루어지며, 상기 바디용 제2도전층 및 제3도전층은 박막 트랜지스터의 바디를 구성하는 것을 특징으로 하는 박막 트랜지스터 구조.A gate of the thin film transistor formed on the semiconductor substrate; A gate insulating film formed on an entire surface of the gate and the substrate and having a contact hole in a portion of the gate; A second conductive layer for a body formed on the gate insulating film; And a third conductive layer for a body formed on the entire surface of the second conductive layer for the body where the contact hole is formed, wherein the second conductive layer and the third conductive layer for the body constitute a body of a thin film transistor. Thin film transistor structure. 제1항에 있어서, 상기 게이트 절연막은 산화막, 산화막/질화막의 이중막, 및 산화막/질화막/산화막의 3중막 중에서 선택된 어느 하나로 구성하는 것을 특징으로 하는 박막 트랜지스터 구조.The thin film transistor structure according to claim 1, wherein the gate insulating film is formed of any one selected from an oxide film, a double film of an oxide film / nitride film, and a triple film of an oxide film / nitride film / oxide film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950000851A 1995-01-19 1995-01-19 Thin film transistor KR0151020B1 (en)

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KR960030445A true KR960030445A (en) 1996-08-17
KR0151020B1 KR0151020B1 (en) 1998-10-01

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