KR960030241A - Distribution type refresh mode control circuit - Google Patents

Distribution type refresh mode control circuit Download PDF

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Publication number
KR960030241A
KR960030241A KR1019950000089A KR19950000089A KR960030241A KR 960030241 A KR960030241 A KR 960030241A KR 1019950000089 A KR1019950000089 A KR 1019950000089A KR 19950000089 A KR19950000089 A KR 19950000089A KR 960030241 A KR960030241 A KR 960030241A
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KR
South Korea
Prior art keywords
combining means
mode
signal
power supply
logical
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KR1019950000089A
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Korean (ko)
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KR0172233B1 (en
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김관언
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019950000089A priority Critical patent/KR0172233B1/en
Publication of KR960030241A publication Critical patent/KR960030241A/en
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Publication of KR0172233B1 publication Critical patent/KR0172233B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4065—Low level details of refresh operations

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

본 발명은 분배형 리프레쉬 모드의 제어회로는, 전 메모리 셀을 리프레쉬하는 연속형 리프레쉬 모드의 동작시 일정한 주기로 한 워드라인씩을 리프레쉬하는 분배형 리프레쉬 모드의 동작을 제거함으로써, 불필요한 전력의 소모를 방지한다. 이를 위하여, 외부로부터 전 메모리 셀을 리프레쉬하는 모드의 제어신호 및 디램의 동작 전원에 따른 제1감지신호 및 일정한 주기로 한 워드라인씩 리프레쉬 하는 모드의 제1제어신호를 논리조합하는 제1논리조합수단과, 외부로부터 전 메모리셀을 리프레쉬 하는 모드의 제어신호 및 디램의 동작전원에 따른 제2 감지신호 및 일정한 주기로 한 워드라인씩 리프레쉬 하는 모드의 제2제어신호를 논리조합하는 제2논리조합수단과, 상기 제1논리조합부 및 상기 제2논리조합부로부터의 신호를 논리조합하는 제3논리조합수단을 구비한다.According to the present invention, the control circuit in the distributed refresh mode eliminates unnecessary power consumption by eliminating the distributed refresh mode in which word lines are refreshed at regular intervals during the continuous refresh mode in which all memory cells are refreshed. . To this end, the first logical combination means for logically combining the control signal of the mode for refreshing all memory cells from the outside, the first detection signal according to the operating power of the DRAM and the first control signal for the mode of refreshing word lines at regular intervals And second logic combining means for logically combining the control signal of the mode for refreshing all memory cells from the outside, the second detection signal according to the operating power of the DRAM, and the second control signal for the mode for refreshing word lines at regular intervals; And third logical combining means for logically combining the signals from the first logical combining unit and the second logical combining unit.

Description

분배형 리프레쉬 모드 제어회로Distribution type refresh mode control circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명의 실시예에 따른 분배형 리프레쉬 모드 제어회로의 회로도, 제5도는 제4도에 도시된 회로의 입·출력 파형도.4 is a circuit diagram of a distributed refresh mode control circuit according to an embodiment of the present invention, and FIG. 5 is an input / output waveform diagram of the circuit shown in FIG.

Claims (5)

외부로부터 전 메모리 셀을 리프레쉬 하는 모드의 제어신호 및 디램의 동작전원에 따른 제1전원전압감지신호 및 제1클럭신호를 논리조합하는 제1논리조합수단과, 외부로부터 전 메모리 셀을 리프레쉬 하는 모드의 제어신호 및 디램의 동작전원에 따른 제2전원전압감지신호 및 일정한 주기로 한 워드라인씩 리프레쉬 하는 모드의 제2클럭신호를 논리조합하는 제2논리조합수단과, 상기 제1논리조합수단 및 상기 제2논리조합수단으로부터의 신호를 논리조합하여 분배형 리프레쉬 모드의 동작을 제어하는 신호를 발생하는 제3논리조합수단을 구비한 것을 특징으로 하는 분배형 리프레쉬 모드의 제어회로.A first logic combining means for logically combining a control signal of a mode for refreshing all memory cells from the outside, a first power voltage sensing signal and a first clock signal according to an operating power supply of the DRAM, and a mode for refreshing all memory cells from the outside Second logic combining means for logically combining a control signal of the second power supply and a second power supply voltage sensing signal according to an operating power supply of the DRAM, and a second clock signal in a mode of refreshing word lines at regular intervals, the first logic combining means, and the And a third logical combining means for generating a signal for controlling the operation of the distributed refresh mode by logically combining the signals from the second logical combining means. 제1항에 있어서, 상기 제1논리조합수단으로부터의 신호를 반전하여 상기 제3논리조합수단쪽으로 매칭하는 제1인버터와, 상기 제2논리조합수단으로부터의 신호를 반전하여 상기 제3논리조합수단쪽으로 매칭하는 제2인버터와, 상기 제3논리조합수단으로부터의 신호를 반전하여 디스트모드쪽으로 매칭하는 제3인버터를 추가로 구비한 것을 특징으로 하는 분배형 리프레쉬 모드의 제어회로.2. The apparatus of claim 1, further comprising: a first inverter for inverting a signal from said first logical combining means and matching toward said third logical combining means, and inverting a signal from said second logical combining means for said third logical combining means; And a second inverter matching the side and a third inverter inverting the signal from the third logical combining means and matching the signal toward the disc mode. 제1항에 있어서, 상기 제1전원전압감지신호가 일정레벨의 제1전원전압이 공급될 경우에 특정논리를 유지하며, 상기 제2전원감지신호가 상기 제1전원전압보다 낮은 레벨의 제2전원전압이 공급될 경우에 특정논리를 유지하는 것을 특징으로 하는 분배형 리프레쉬 모드의 제어회로.2. The method of claim 1, wherein the first power supply voltage detection signal maintains a specific logic when a first power supply voltage having a predetermined level is supplied, and the second power supply detection signal has a lower level than the first power supply voltage. A control circuit in a distributed refresh mode, characterized by maintaining a specific logic when a power supply voltage is supplied. 제1항에 있어서, 상기 제3논리조합수단이 NOR 게이트를 포함한 것을 특징으로 하는 분배형 리프레쉬 모드의 제어회로.2. The control circuit according to claim 1, wherein said third logical combining means comprises a NOR gate. 제1항에 있어서, 상기 제1논리조합수단 및 제2논리조합수단이 NAND 게이트를 포함한 것을 특징으로 하는 분배형 리프레쉬 모드의 제어회로.2. The distributed refresh mode control circuit as claimed in claim 1, wherein the first logical combining means and the second logical combining means comprise a NAND gate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950000089A 1995-01-05 1995-01-05 Distribution type refresh mode control circuit KR0172233B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950000089A KR0172233B1 (en) 1995-01-05 1995-01-05 Distribution type refresh mode control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950000089A KR0172233B1 (en) 1995-01-05 1995-01-05 Distribution type refresh mode control circuit

Publications (2)

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KR960030241A true KR960030241A (en) 1996-08-17
KR0172233B1 KR0172233B1 (en) 1999-03-30

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