KR960030228A - Step-up circuit including logic element - Google Patents

Abstract

The present invention relates to a booster circuit including a logic element, which processes the decoding of the signal itself in a level shifter directly without passing through a logical-inverting device or a logic-sum inverting device, thereby providing a simplification and speed improvement of the circuit.

Such a boosting circuit including a logic device of the present invention includes decoding means for decoding and outputting at least two or more input bits; Inverting means for inverting and outputting the number of input bits; It is achieved by the level shifter means for switching along the voltage level obtained by the decoding means and the inverting means to boost the voltage of the power supply terminal and provide it to the word line.

Description

Step-up circuit including logic element

Since this is an open matter, no full text was included.

2 is a step-up circuit diagram including a logic element of the present invention, (a) is a level shifter circuit diagram including an AND logic inverting element, (B) is a level shifter circuit diagram including an OR sum inversion element, and (C) is a logic multiplication element A level shifter circuit diagram is included, and (d) is a level shifter circuit diagram including a logic sum element.

Claims (15)

Decoding means for decoding and outputting at least two input bit numbers; and inverting means for inverting and outputting the different number of input bits; and boosting a voltage of a power supply terminal according to a voltage level obtained by the decoding means and the inversion means. And a level shifting means provided in the step-up circuit. The N-MOS transistor of claim 1, wherein the decoding means has a gate connected to the different input terminals and controls the output voltage of the level shifter means supplied to the word line according to the level of the input signal. Step-up circuit including a logic element characterized in that consisting of NM3). 3. The booster circuit according to claim 1 or 2, wherein the decoding means is an AND-inverting element. 3. The booster circuit according to claim 1 or 2, wherein the decoding means is a logic sum inverting element. The booster circuit according to claim 1 or 2, wherein the decoding means is a logical multiplication device. 3. The booster circuit according to claim 1 or 2, wherein the decoding means is a logic sum element. 4. The PMOS transistor of claim 3, wherein the level shifter means comprises: a P-MOS transistor (PM2) whose gate is connected to a drain of an N-most transistor (NM1) of the decoding means and switched; A P-MOS transistor (PM1) connected in parallel with the P-MOS transistor (PM2) and connected in series with the N-MOS transistor (PM1) to provide a voltage of a power supply terminal to an output terminal; N-MOS transistors NM4 to NM6 connected in series with the P-MOS transistor PM2 and switched according to different voltage levels obtained by the inversion means to control the gate of the P-MOS transistor PM1. Step-up circuit including a logic element characterized in that. The level shifter means when the decoding means is a logic sum inverting element. The level shifter means is configured by connecting the N-MOS transistors NM4 to NM6 in parallel with an output terminal and in series with a P-MOS transistor. Step-up circuit including a logic element. 5. The method of claim 4, wherein when the decoding means is a logical sum inversion element, different input terminals are connected to the gates of the N-MOS transistors NM4 to NM6 connected in series, and different voltages inverted by the inversion means are N-MOS. A boosting circuit including a logic element, characterized in that configured to be applied to transistors NM1 to NM3. 6. The method of claim 5, wherein when the decoding means is a logical multiplication device, different input terminals are connected to the gates of the N-MOS transistors NM1 to NM3 connected in series, and different voltages inverted to the inverting means are N-MOS transistors. A booster circuit including a logic element characterized in that it is connected to the gates of NM4 to NM6. 6. The level shifter means according to claim 5, wherein the level shifter means when the decoding means is a logical multiplication device is configured by connecting the N-MOS transistors NM4 to NM6 in parallel with an output terminal and directly connecting the P-MOS transistor. Step-up circuit including a logic element. 7. The method of claim 6, wherein when the decoding means is a logic element, different input terminals are connected to gates of the N-MOS transistors NM4 to NM6 connected in series, and different voltages inverted by the inverting means are N-MOS transistors NM1. A boosting circuit including a logic element characterized in that it is connected to the gate of ~ NM3). 7. The level shifter in the case where the decoding means is a logic element, and is connected in parallel with the output terminals of the N-MOS transistors NM4 to NM6 and connected in series with the P-MOS transistor PM2. Step-up circuit including a logic element. A logical AND inversion element for logically inverting and outputting two signal bits among at least three or more bits; A first inverting element for inverting an output signal of the AND product; A second inversion device for inverting the other bit; The N-MOS transistors NM27 (NM28) and the P-MOS transistor PM9 are switched to supply power to a word line according to the output signals of the AND-inverting device and the second inverting device, and the first inverting device and the other are inverted. The N-MOS transistor NM25, NM26 and P-MOS transistor PM10 are switched by one bit signal, and the voltage supplied to the word line is configured as a level shifter means for controlling the word line. Booster circuit including element. 15. The boost circuit according to claim 14, wherein a signal directly input to the level shifter means among at least three or more bits is at a slower speed than the two bit signals. ※ Note: The disclosure is based on the initial application.