KR960028452A - MP-2 Demultiplexer - Google Patents

MP-2 Demultiplexer Download PDF

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Publication number
KR960028452A
KR960028452A KR1019940035037A KR19940035037A KR960028452A KR 960028452 A KR960028452 A KR 960028452A KR 1019940035037 A KR1019940035037 A KR 1019940035037A KR 19940035037 A KR19940035037 A KR 19940035037A KR 960028452 A KR960028452 A KR 960028452A
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South Korea
Prior art keywords
packet
signal
data
demultiplexer
parallel
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KR1019940035037A
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Korean (ko)
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KR0137558B1 (en
Inventor
이동호
문영식
호요성
안치득
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양승택
재단법인 한국전자통신연구소
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Priority to KR1019940035037A priority Critical patent/KR0137558B1/en
Publication of KR960028452A publication Critical patent/KR960028452A/en
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Publication of KR0137558B1 publication Critical patent/KR0137558B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
    • H04N21/4344—Remultiplexing of multiplex streams, e.g. by modifying time stamps or remapping the packet identifiers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/236—Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
    • H04N21/23608—Remultiplexing multiplex streams, e.g. involving modifying time stamps or remapping the packet identifiers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/242—Synchronization processes, e.g. processing of PCR [Program Clock References]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/426—Internal components of the client ; Characteristics thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
    • H04N21/4347—Demultiplexing of several video streams

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

본 발명은 MPEG-2역다중화기에 관한 것으로, 다중화된 직렬 비트 스트림을 입력받아 소정 비트씩의 병렬 형태인 병렬 데이타로 변환하여 출력하는 바이트 정렬 직력/병렬 변환부(6)와, 패킷 구별신호(PID)에 따라 상기 병렬 데이타를 입력받아TS 패킷을 해석하여 PES 패킷의 내용을 구분해주는 구별 위도우 신호 및 클럭을 복원하기 위한 PCR을 출력하는 TS 패킷 역다중화부(8)와, 상기 병렬 데이타에서 프로그램에 관한 정보를 해석해서 상기 패킷 구별신호(PID)를 초기화하는 PSI 처리부(10)와, 상기 병렬 데이타 및 상기 구별 윈도우 신호를 PES 패킷 해석하여 위상이 조절된 데이타, 윈도우 신호, DTS,PTS 기준 신호를 출력하는 PES 패킷 역다중화부(9)와, 상기 PCR에 따라 시스템 클럭을 복원하는 윈도우 클럭 복원부(11)를 구비하는 것을 특징으로 하여 입력되는 디지탈 데이타로 부터 압축된 영상, 음성 및 데이타를 분리해내는, 특히 MPEG-2에서 제안하는 시스템 규격을 만족하도록 동작할 수 있는 효과가 있다.The present invention relates to an MPEG-2 demultiplexer, comprising: a byte alignment serial / parallel converter (6) for receiving a multiplexed serial bit stream and converting the result into parallel data in parallel form by predetermined bits; A TS packet demultiplexer 8 for receiving the parallel data according to PID) and outputting a PCR for restoring a clock and a distinguishing Widow signal for distinguishing the contents of the PES packet by interpreting the TS packet; A PSI processing unit 10 for initializing the packet discrimination signal (PID) by analyzing the information about the PES packet, and the phase-adjusted data, window signal, DTS, and PTS reference signal by analyzing the parallel data and the discrimination window signal. And a PES packet demultiplexer 9 for outputting a signal, and a window clock recoverer 11 for restoring a system clock according to the PCR. To separate the video, audio and data compression from itaconic, in particular there is an effect capable of operating so as to satisfy the system standard proposed by the MPEG-2.

Description

엠피이지-2 역다중화기MP-2 Demultiplexer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 2 도는 본 발명에 따른 MPEG-2 역다중화기의 블럭도, 제 3 도는 제 2 도의 TS(Transport Stream)패킷 역다중화부의 상세 블럭도, 제 4 도는 제 2 도의 PES(Packetized Elementery Stream)패킷 역다중화부의 상세 블럭도.2 is a block diagram of an MPEG-2 demultiplexer according to the present invention, FIG. 3 is a detailed block diagram of a TS (Transport Stream) packet demultiplexer of FIG. 2, and FIG. 4 is a packetized elementery stream (PES) packet demultiplexing of FIG. Negative detailed block diagram.

Claims (6)

다중화된 직렬 비트 스트림을 입력받아 소정 비트씩의 병렬 형태인 병렬 데이타로 변환하여 출력하는 바이트 정렬 직렬/병렬 변환부(6)와, 패킷 구별신호(PID)에 따라 상기 병렬 데이타를 입력받아 TS 패킷을 해석하여 PES 패킷의 내용을 구분해주는 구별 윈도우신호 및 클럭을 복원하기 위한 PCR을 출력하는 TS 패킷 역다중화부(8)와, 상기 병렬 데이타에서 프로그램에 관한 정보를 해석해서 상기 패킷 구별신호(PID)를 초기화하는 PSI(Program Specific Information) 처리부(10)와, 상기 병렬 데이타 및 상기 구별 윈도우 신호를 PES 패킷 해석하여 위상이 조절된 데이타, 윈도우 신호, DTS, PTS 기준 신호를 출력하는 PES 패킷 역다중화부(9)와, 상기 PCR에 따라 시스템 클럭을 복원하는 윈도우 클럭 복원부(11)를 구비하는 것을 특징으로 하는 MPEG-2 역다중화기A byte-aligned serial / parallel converter 6 for receiving a multiplexed serial bit stream and converting it into parallel data in parallel form by predetermined bits and the TS packet by receiving the parallel data according to a packet discrimination signal (PID) A TS packet demultiplexer 8 for outputting a discrimination window signal for distinguishing the contents of the PES packet and a PCR for restoring the clock, and the packet discrimination signal (PID) by analyzing information about a program in the parallel data. PES (Program Specific Information) processing unit 10 for initializing the PES packet, and PES packet demultiplexing for outputting phase-adjusted data, window signals, DTS, and PTS reference signals by analyzing the parallel data and the distinguished window signal. MPEG-2 demultiplexer, characterized in that it comprises a section 9 and a window clock recovery section 11 for restoring the system clock in accordance with the PCR. 제 1 항에 있어서, 상기 PES 패킷 역다중화부(9)로부터 출력되는 데이타를 직렬 데이타로 변환하는 병렬/직렬 변환부(12)를 더 구비하는 것을 특징으로 하는 MPEG-2 역다중화기.The MPEG-2 demultiplexer according to claim 1, further comprising a parallel / serial conversion section (12) for converting data output from said PES packet demultiplexing section (9) into serial data. 제 1 항에 있어서, 상기 바이트 정렬 직렬/병렬 변환부(6)는, 상기 입력받는 직렬 비트 스트림을 MPEG-2 시스템 신택스의 바이트 단위에 맞춰 8 비트 병렬 신호로 변환하도록 구성되는것을 특징으로 하는 MPEG-2 역다중화기.2. The MPEG apparatus according to claim 1, wherein the byte-aligned serial / parallel converter 6 is configured to convert the received serial bit stream into an 8-bit parallel signal in accordance with byte units of MPEG-2 system syntax. -2 demultiplexers. 제 1 항에 있어서, 상기 TS 패킷 역다중화부(8)는, 상기 병렬 데이타중 TS 패킷에서 동기 바이트를 검출하는 동기 바이트 검출부(13)와, 상기 동기 바이트에 따라 카운트하여 TS 패킷의 끝점 신호를 출력하는 188 바이트 카운터(14)와, 상기 동기 바이트에 따라 상기 병렬 데이타의 헤더를 해석해서 헤더 정보를 출력하는 제 1 헤더 처리부(15)와, TS 패킷에서 시스템 클럭을 복원하기 위해 필요한 PCR을 출력하는 적응 필드 처리부(16)와, 상기 188 바이트 카운터(14), 헤더 처리부(15), 적응 필드 처리부(16)의 출력에 따라 상기 병렬 데이타를 처리하여 위상이 보상된 구별 윈도우 신호를 출력하는 데이타 바이트 처리부(17)를 구비하는것을 특징으로 하는 MPEG-2 역다중화기.2. The TS packet demultiplexer (8) according to claim 1, wherein the TS packet demultiplexer (8) comprises: a sync byte detector (13) for detecting a sync byte in a TS packet of the parallel data, and counting according to the sync byte to output an end point signal of the TS packet. An output 188 byte counter 14, a first header processor 15 for analyzing the header of the parallel data according to the sync byte, and outputting header information, and a PCR required for restoring a system clock from a TS packet; Data for processing the parallel data according to the output of the adaptive field processor 16, the 188 byte counter 14, the header processor 15, and the adaptive field processor 16 to output a phase-compensated distinct window signal. An MPEG-2 demultiplexer characterized by comprising a byte processing unit (17). 제 1 항에 있어서, 상기 PES 패킷 역다중화부(9)는, 상기 병렬 데이타를 입력받아 PES 패킷의 시작점 및 형태 정보를 검출하는 PES 패킷 정보 검출부(18)와, 상기 구별 윈도우 신호를 입력받아 상기 PES 패킷의 시작점 및 형태 정보에 따라 헤더를 해석해서 PES 패킷의 헤더 및 데이타의 길이 정보를 검출하고, 카운트 제어신호를 발생시키는 제 2 헤더 처리부(19)와, 상기 카운트 제어신호에 따라 비디오, 오디오, 데이타 정보가 PES 패킷에서 시작되는 기준신호인 패이로드 시작 정보를출력하는 8 비트 카운터(22)와, 상기 PES 패킷의 시작점 및 형태 정보, 상기 구별 윈도우 신호에 따라 최종 윈도우 신호를 출력하는 데이타 윈도우 발생부(21)와, 상기 제 2 헤더 처리부(19)의 출력에 따라 상기 병렬 데이타에서 DTS 및 PTS를 찾은 후 예정된 출력 포멧으로 변환하여 출력하는 DTS. PTS 출력 처리부(20)를 구비하는 것을 특징으로 하는 MPEG-2 역다중화기.The PES packet demultiplexing unit (9) according to claim 1, wherein the PES packet demultiplexing unit (9) receives the parallel data and detects the starting point and shape information of the PES packet, and receives the distinguishing window signal. A second header processor 19 for analyzing the header according to the start point and shape information of the PES packet to detect the header and data length information of the PES packet, and generating a count control signal; and video and audio according to the count control signal. And an 8-bit counter 22 for outputting payload start information in which data information is a reference signal starting from a PES packet, and a data window for outputting a final window signal according to the start point and shape information of the PES packet and the distinguishing window signal. The D21 and PTS are found in the parallel data according to the output of the generator 21 and the second header processor 19, and then converted into a predetermined output format. DTS. MPEG-2 demultiplexer characterized in that it comprises a PTS output processing section (20). 제 1 항에 있어서, 상기 시스템 클럭 복원부(11)는, 상기 PCR에 따라 27MHz 클럭과 LPCR을 출력하도록 구성되는 MPEG-2 역다중화기.The MPEG-2 demultiplexer according to claim 1, wherein the system clock recovery unit (11) is configured to output a 27 MHz clock and an LPCR according to the PCR. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940035037A 1994-12-19 1994-12-19 Mpeg-2 inverse multiplexer KR0137558B1 (en)

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KR1019940035037A KR0137558B1 (en) 1994-12-19 1994-12-19 Mpeg-2 inverse multiplexer

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KR960028452A true KR960028452A (en) 1996-07-22
KR0137558B1 KR0137558B1 (en) 1998-05-15

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100545454B1 (en) * 1997-04-04 2006-10-19 해리스 코포레이션 Digital signal system with synchronous trust counter
KR100749070B1 (en) * 2000-07-14 2007-08-13 삼성전자주식회사 System for de-multiplexing TS

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100545454B1 (en) * 1997-04-04 2006-10-19 해리스 코포레이션 Digital signal system with synchronous trust counter
KR100749070B1 (en) * 2000-07-14 2007-08-13 삼성전자주식회사 System for de-multiplexing TS

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