JP2004120632A - System and method for data analysis - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively analysis data of predetermined bit number following a start code without unnecessary load to an analysis means. <P>SOLUTION: First, a start code detector 21 detects a start code. The start code detector 21 supplies an input data signal to a delay circuit 22 every time one byte data are supplied. The start code detector 21 supplies "1" as the input data signal to the delay circuit 22 when a start code is recognized, and supplies "0" when not recognized. The delay circuit 22 recognizes the bit number of data inputted to the start code detector 21 following the start code by memorizing the supplied input data signal one by one to a shift register. When all separation data are inputted to the start code detector 21, it supplies a start code detection signal to a detection position storing part 24, and the detection position storing part 24 supplies a position signal to a data analysis part 4. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data analysis method used when multiplexing video coded data and audio coded data and separating the multiplexed data in, for example, an MPEG (Moving Picture Expert Group) system. The present invention relates to a system and a data analysis method.
[0002]
[Prior art]
2. Description of the Related Art In recent years, digital transmission systems using digital broadcasting media and digital communication media as transmission media generally adopt a digital multiplexing method using an MPEG system, which is one of compression and multiplexing standards for audio information and image information. ing.
[0003]
MPEG is defined as ISO / IEC JTC1 / SC29 (International Organization / International Electrotechnical Commission, Joint Technical Committee / Sub Committee / 29). This is an abbreviation of a moving picture expert group for coding. For example, ISO11172 is standardized as the MPEG1 standard, and ISO13818 is standardized as the MPEG2 standard. In the following, the international standard for moving picture coding defined by MPEG is referred to as MPEG.
[0004]
Hereinafter, a digital multiplex transmission system based on MPEG2-PS (Program Stream) will be described. As shown in FIG. 6, the digital multiplex transmission system 100 based on MPEG2-PS includes a transmission system 101, a reception system 102, and a transmission path 103.
[0005]
The transmission system 101 includes an audio encoder 111, a video encoder 112, an audio encode buffer 113, a video encode buffer 114, and a multiplexer 115.
[0006]
The audio encoder 111 receives, for example, a digital audio signal collected by a microphone, an audio signal reproduced from a recording medium, and the like. The audio encoder 111 compresses and encodes the input digital audio signal based on the MPEG2-PS standard to generate encoded audio data. The generated audio encoded data is stored in the audio encode buffer 113.
[0007]
For example, a digital video signal captured by a camera or a digital video signal reproduced from a recording medium is input to the video encoder 112. The video encoder 112 compression-encodes the input digital video signal based on the MPEG2 standard to generate encoded video data. The generated encoded video data is stored in the video encoding buffer 114.
[0008]
The audio encode buffer 113 temporarily stores the supplied encoded audio data until the audio encoded data is read out by the multiplexer 115.
[0009]
The video encoding buffer 114 temporarily stores the supplied encoded video data until it is read by the multiplexer 115.
[0010]
The multiplexer 115 multiplexes the audio encoded data stored in the audio encode buffer 113 and the video encoded data stored in the video encode buffer 114, and generates a PES (Program Elementary Stream) packet defined by the MPEG2-PS standard. Generate
[0011]
As shown in FIG. 1, the PES packet has a configuration in which a header is added to the head of packet data such as audio encoded data and video encoded data. The header includes a 3-byte start code indicating the start of the PES packet, a 1-byte stream ID indicating the contents of the packet data, a 2-byte PES packet length indicating the length of data following this area, a 2-byte flag, It contains the PES header data length in bytes and the PES header data. The PES header data and the packet data are variable in the number of bytes.
[0012]
Then, the multiplexer 115 generates a pack by adding a pack header to the beginning of one or more PES packets, and generates a program stream (hereinafter, referred to as PS) by connecting the packs.
[0013]
When generating a PES packet, the multiplexer 115 outputs, for each reproduction unit called an access unit, DTS (Decoding Time Stamp) which is time information indicating a decoding time and PTS which is time information indicating a reproduction output time. A time stamp called (Presentation TimeStamp) is added. DTS and PTS are included in PES header data.
[0014]
The multiplexer 115 also adds an SCR (System Clock Reference) when generating a pack. The SCR is information for setting an STC (System Time Clock), which is a reference synchronization clock used at the time of decoding, to an intended value in the receiving system 102. The SCR is included in the pack header.
[0015]
On the other hand, the receiving system 102 includes a separator 121, an audio decode buffer 122, a video decode buffer 123, an audio decoder 124, and a video decoder 125.
[0016]
The separator 121 determines, based on the stream ID described in the supplied PES packet, whether the packet data included in the PES packet is video encoded data, audio encoded data, or the like. When the packet data included in the PES packet is video encoded data, the separator 121 stores the data in the video decode buffer, and when the packet data is audio encoded data, stores the data in the audio decode buffer.
[0017]
The audio decode buffer 122 temporarily stores the supplied encoded audio data until the data is read by the audio decoder 124.
[0018]
The video decode buffer 123 temporarily stores the supplied encoded video data until the data is read by the video decoder 125.
[0019]
The audio decoder 124 reads out the encoded audio data stored in the audio decode buffer 122 for each access unit, decodes the data according to the MPEG2-PS standard, and generates an audio signal. The audio decoder 124 decodes and outputs the encoded audio data at the timing when the STC and the PTS match.
[0020]
The video decoder 125 reads out the encoded video data stored in the video decode buffer 122 for each access unit, decodes the data according to the MPEG2-PS standard, and generates a video signal. The video decoder 125 decodes the encoded video data at the timing when the STC matches the DTS, and outputs the decoded video signal at the timing when the STC matches the PTS.
[0021]
In the digital multiplex transmission system described above, each data stream such as PES packets, audio encoded data, and video encoded data is analyzed. Each data stream is composed of a packet, and has a configuration in which a packet header is added to the head of the packet. The start of the packet header is a start code, and the position following the start code includes data on the length of the stream, the analysis method, and the like. When analyzing the data stream, after detecting a start code, the packet header data is analyzed to read the analysis method and length of the packet data, and to process the packet data according to the read result.
[0022]
Hereinafter, a method in which the separator 121 analyzes the packet header of the PES packet and supplies the packet data to the audio decode buffer 122 or the video decode buffer 123 will be described in detail.
[0023]
As shown in FIG. 7, the separator 121 includes a data buffer 130, a start code detection unit 131, and a data analysis unit 132.
[0024]
First, the data stream is stored in the data buffer 130. Next, the start code detecting unit 131 searches the data buffer 130 for data stored therein.
[0025]
Next, when the start code is detected, the start code detection unit 131 notifies the data analysis unit 132 that the start code has been detected.
[0026]
Next, the data analysis unit 132 accesses the data buffer 130 and confirms that all data of the packet header has been stored in the data buffer 130.
[0027]
The data analysis unit 132 analyzes the packet header to determine the type of the packet data, and when the packet data is video encoded data, supplies the packet data to the video decode buffer 123 and outputs the audio encoded data. If so, the packet data is supplied to the audio decode buffer 124.
[0028]
[Problems to be solved by the invention]
The data analysis unit 132 starts analyzing the data of the packet header after all the data of the packet header is stored in the data buffer 130. The process until the data analysis unit 132 starts analyzing the data of the packet header is as shown in FIG. 8 below.
[0029]
First, in step S1, the start code detector 131 detects a start code from the input data and notifies the data analyzer 132 of the start code.
[0030]
Next, in step S2, the data analysis unit 132 accesses the data buffer 130 and determines whether or not all data of the packet header is stored in the data buffer 130. If all the data of the packet header is stored in the data buffer 130, the process proceeds to step S3, and if not, the operation of step S2 is performed again.
[0031]
Then, in step S3, the data analysis unit 132 starts analyzing the data of the packet header.
[0032]
That is, the data analysis unit 132 needs to repeatedly access the data buffer 130 after the start code is detected until all the packet headers are stored.
[0033]
However, in the receiving system 103, as shown in FIG. 9, there is a case where the packet header is intermittently supplied to the separator 121. When the packet header is intermittently supplied to the separator 121, it takes a long time until all the packet headers are stored in the data buffer 130.
[0034]
Therefore, the number of times that the data analysis unit 132 accesses the data buffer 130 increases. When the number of times that the data analysis unit 132 accesses the data buffer 130 is large, the load on the data analysis unit 132 increases. Further, the time required for the data analysis unit 132 to analyze the packet header also increases.
[0035]
The present invention has been proposed in view of the conventional situation described above, and header data of a predetermined number of bits following a start code is stored in the storage unit without the analysis unit accessing the storage unit a plurality of times. An object of the present invention is to provide a data analysis system and a data analysis method capable of efficiently performing processing on a data stream by determining that the data stream has been stored.
[0036]
[Means for Solving the Problems]
In the data analysis system according to the present invention, a data stream composed of a plurality of packets is sequentially input, and in the data analysis system for analyzing the data stream, a start code indicating the head of the packet is detected from the input data stream. A packet data storage unit for sequentially storing the data stream; and a header data of a predetermined number of bits following the start code is stored in the packet data storage unit based on a timing at which the detection unit detects a start code. Timing generation means for generating the timings stored for the packet data storage means, and analysis means for analyzing a predetermined number of bits of header data following the start code among the data stored in the packet data storage means. Wherein the analysis means is Based on the timing of the timing generating means is generated, characterized in that starting the analysis of the header data of the predetermined number of bits subsequent to the start code.
[0037]
In the data analysis system according to the present invention, based on the timing at which the detection unit outputs the start code detection signal, the timing generation unit stores all the header data of a predetermined number of bits following the start code in the packet data storage unit. Detected timing. Then, the analysis means starts analyzing header data of a predetermined number of bits following the start code based on the timing at which the timing generation means outputs the start code detection signal.
[0038]
Further, in the data analysis method according to the present invention, in the data analysis method for sequentially inputting a data stream composed of a plurality of packets, and analyzing the data stream, a start code indicating a head of the packet from the input data stream Detection step, a storage step of sequentially storing the data stream in storage means, and header data of a predetermined number of bits following the start code based on a timing at which a start code is detected in the detection step. Generating a timing stored in the packet data storage means, and analyzing a predetermined number of bits of header data following the start code in the data stored in the storage means. Analyzing step, In analysis step, based on the timing of the start code detection signal is output at the timing generating step, characterized in that starting the analysis of the header data of the predetermined number of bits subsequent to the start code.
[0039]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Hereinafter, an example will be described in which the present invention is applied to a PES (Sequence Elementary Stream) packet separator that separates data included in a packet.
[0040]
As shown in FIG. 1, the PES packet has a configuration in which a header is added to the head of packet data such as audio encoded data and video encoded data. The header includes a 3-byte start code indicating the start of the PES packet, a 1-byte stream ID indicating the contents of the packet data, a 2-byte PES packet length indicating the length of data following this area, a 2-byte flag, It contains the PES header data length in bytes and the PES header data. The PES header data and the packet data are variable in the number of bytes.
[0041]
In the present embodiment, a stream ID, a PES packet length, a flag, a PES header data length, a PTS, and a DTS in a PES packet are referred to as separated data. By analyzing the separated data, it becomes possible to know the type and time stamp of the packet data, and it is possible to separate the PES packets. Further, as shown in FIG. 1, the separation data has a fixed length.
[0042]
As shown in FIG. 2, the PES packet separator 1 includes an analysis delay unit 2, a data buffer 3, a data analysis unit 4, and a DMA transfer unit 5. The PES packet separator 1 is connected to an audio decode buffer 6 and a video decode buffer 7. The PES packet separator 1 separates a PES packet of a data stream input from the outside into one in which packet data is audio encoded data and one in which packet data is video encoded data.
[0043]
The analysis delay unit 2 supplies a position signal to the data analysis unit 4 when all the separated data is stored in the data buffer 3, and causes the data analysis unit 4 to start analyzing the separated data. The details of the analysis delay unit 2 will be described later.
[0044]
The data buffer 3 stores data input to the PES packet separator 1.
[0045]
The data analysis unit 4 analyzes the separated data stored in the data buffer 3 based on the position signal supplied from the analysis delay unit 2, and reads the type, position, and decoding method of the packet data. The data analysis unit 4 includes a CPU (Central Processing Unit) 10 and a program storage unit 11 in which a program for analyzing data is stored. When the position signal is supplied from the analysis delay unit 2, the data analysis unit 4 starts the program and starts analyzing the separated data.
[0046]
The DMA transfer unit 5 supplies the packet data to the audio decode buffer 6 when the packet data is audio encoded data, and supplies the packet data to the audio decode buffer 6 when the packet data is video encoded data in accordance with an instruction from the data analysis unit 4. Is supplied to the video decode buffer 7.
[0047]
The audio decode buffer 6 temporarily stores the supplied encoded audio data until the supplied encoded audio data is read by an audio decoder (not shown).
[0048]
The video decode buffer 7 temporarily stores the supplied encoded video data until the supplied encoded video data is read by a video decoder (not shown).
[0049]
Hereinafter, the analysis delay unit 2 will be described in detail.
[0050]
As shown in FIG. 3, the analysis delay unit 2 includes a start code detection unit 21, a delay circuit 22, a position detection unit 23, and a detection position holding unit 24.
[0051]
The start code detection unit 21 detects a start code of a PES packet forming a data stream. Further, each time data is supplied, “1” or “0” is supplied to the delay circuit 22 as a data input signal. More specifically, the start code detection unit 21 supplies “1” to the delay circuit 22 when a start code is detected by inputting data, and when a start code is not detected even when data is input. “0” is supplied to the delay circuit 22. Further, the start code detector 21 supplies a position detection signal to the position detector 23 every time data is input.
[0052]
In the present embodiment, the start code detection unit 21 supplies a data input signal to the delay circuit 22 every time 1-byte data is input, and a position detection signal to the position detection unit 23. Supply. The detailed configuration of the start code detection unit 21 will be described later.
[0053]
The delay circuit 22 operates with the synchronous clock of the data stream, and outputs the start code detection signal with the timing delayed by the number of bytes of the separated data. The detailed configuration of the delay circuit 22 will be described later.
[0054]
The position detector 23 indicates the position of the data stored in the data buffer 3 on the data buffer 3 by incrementing the value by one each time the position detection signal is supplied from the start code detector 21. .
[0055]
The detection position holding unit 24 holds the data of the position detection unit 23 when the start code detection signal is supplied. The held data is supplied to the data analyzer 4 as a position signal.
[0056]
Hereinafter, a detailed configuration of the start code detection unit 21 will be described.
[0057]
For example, as shown in FIG. 4, the start code detection unit 21 includes an AND circuit 41, a first data comparison unit 42a, a second data comparison unit 42b, and a third data comparison unit 42c (hereinafter, collectively referred to as “general name”). The first to third data comparison units 42a to 42c).
[0058]
The AND circuit 41 outputs “1” when all the outputs from the first to third data comparison units 42 a to 42 c are “1”, and outputs the “1” from the first to third data comparison units 42 a to 42 c. When "0" is present in the output of "1", "0" is output.
[0059]
The first to third data comparison units 42a to 42c compare the input data with the data constituting the start code and determine whether or not they match.
[0060]
The first data comparison unit 42a includes a first input data register 51a, a first start code register 52a, a first XOR circuit 53a, a first pattern mask 54a, and a first NAND circuit 55a. Is provided. The second data comparison unit 42b includes a second input data register 51b, a second start code register 52b, a second XOR circuit 53b, a second pattern mask 54b, and a second NAND circuit 55b. Further, the third data comparison unit 42c includes a third input data register 51c, a third start code register 52c, a third XOR circuit 53c, a third pattern mask 54c, and a third NAND circuit 55c.
[0061]
Hereinafter, the first input data register 51a, the second input data register 51b, and the third input data register 51c are collectively referred to as first to third input data registers 51a to 51c. Further, the first start code register 52a, the second start code register 52b, and the third start code register 52c are collectively referred to as first to third start code registers 52a to 52c. Further, the first XOR circuit 53a, the second XOR circuit 53b, and the third XOR circuit 53c are collectively referred to as first to third XOR circuits 53a to 53c. Furthermore, the first pattern mask 54a, the second pattern mask 54b, and the third pattern mask 54c are collectively referred to as first to third pattern masks 54a to 54c. Furthermore, the first NAND circuit 55a, the second NAND circuit 55b, and the third NAND circuit 55c are collectively referred to as first to third NAND circuits 55a to 55c.
[0062]
The first to third input data registers 51a to 51c store the data input to the start code detection unit 21 byte by byte. When one byte of data is input to the start code detection unit 2, the data is stored in the first input data register 51a, and the data stored in the first input data register 51a is stored in the second input data register 51a. The data stored in the input data register 51b and the data stored in the second input data register 51b are stored in the third input data register 51C.
[0063]
The first to third start code registers 52a to 52c store data constituting a start code one byte at a time. More specifically, the first start code register 52a stores the data of the third byte from the top of the data constituting the start code, and the second start code register 52b stores the first byte of the data constituting the start code. The third start code register 52c stores the data of the first byte of the data constituting the start code.
[0064]
The first to third XOR circuits 53a to 53c store the data stored in the first to third input data registers 51a to 51c and the first to third start code registers 52a to 52c. And outputs "0" when they match. More specifically, the first XOR circuit 53a compares the data stored in the first input data register 51a with the data stored in the first start code register 52a, 53b compares the data stored in the second input data register 51b with the data stored in the second start code register 52b, and the third XOR circuit 53c compares the data stored in the third input data register 51c. Is compared with the data stored in the third start code register 52c.
[0065]
The first to third pattern masks 54a to 54c store "1".
[0066]
The first to third NAND circuits 55a to 55c are used to output the signals output from the first to third XOR circuits 53a to 53c and the signals stored for the first to third pattern masks 54a to 54c. And outputs “1” when “0” is output from the first to third XOR circuits 53a to 53c.
[0067]
The operation of the start code detecting unit 21 described above is as described below.
[0068]
First, when 1-byte data is input to the start code detection unit 21, the input data is stored in the first input data register 51a. The data stored in the first input data register 51a is stored in the second input data register 51b, and the data stored in the second input data register 51b is stored in the third input data register 51b. The data is stored in the input data register 51c.
[0069]
Next, the first XOR circuit 53a outputs “0” when the data stored in the first input data register 51a matches the data stored in the first start code register 52a. If they do not match, "1" is output.
[0070]
Further, the second XOR circuit 53b outputs “0” when the data stored in the second input data register 51b matches the data stored in the second start code register 52b. If they do not match, "1" is output.
[0071]
Further, the third XOR circuit 53c outputs “0” when the data stored in the third input data register 51c matches the data stored in the third start code register 52c. If they do not match, "1" is output.
[0072]
Next, the first NAND circuit 55a outputs “1” when the first XOR circuit 53a outputs “0”, and outputs “0” when the first XOR circuit 53a outputs “1”. Output.
[0073]
The second NAND circuit 55b outputs “1” when the second XOR circuit 53b outputs “0”, and outputs “0” when the second XOR circuit 53b outputs “1”. I do.
[0074]
Further, the third NAND circuit 55c outputs “1” when the third XOR circuit 53c outputs “0”, and outputs “0” when the third XOR circuit 53c outputs “1”. I do.
[0075]
Then, the AND circuit 41 outputs “1” only when “1” is output from all of the first to third NAND circuits 55a to 55c, and the AND circuit 41 outputs the “1” to the first to third NAND circuits 55a to 55c. When "0" is output from one or more of them, "0" is output. “1” and “0” output from the AND circuit 41 are supplied to the delay circuit 22 as input data signals.
[0076]
As described above, the start code detection unit 21 detects a start code every time one byte of data is input, and supplies an input data signal to the delay circuit 22.
[0077]
Hereinafter, the configuration of the delay circuit 22 will be described in detail.
[0078]
As shown in FIG. 5, for example, as shown in FIG. 5, the delay circuit 22 adjusts the delay amount when the number of bytes of the separated data is different, and registers 31-1, 31-2, 31- for storing the input data signal. 3,... 31- (n-1) and 31-n (n is a natural number). The delay circuit 22 operates with a synchronous clock of the data stream.
[0079]
That is, the delay circuit 22 delays the start code detection signal by the number of bytes of the separated data and outputs the result. The delay circuit 22 supplies a start code detection signal to the detection position holding unit 24 when a data input signal is supplied from the start code detection unit 21 in a state where “1” is stored in the register 31-1. I do.
[0080]
The operation of the PES packet separator 1 described above is as described below.
[0081]
First, data constituting a PES packet is sequentially input to the PES packet separator 1. The supplied data is supplied to the analysis delay unit 2 and stored in the data buffer 3.
[0082]
The data supplied to the analysis delay unit 2 is stored in the first input data buffer 51a provided in the start code detection unit 21 for each byte. In the start code detecting unit 21, when new data is stored in the first input data buffer 51a, the data stored in the first input data buffer 51a is replaced with the second input data buffer 51a. The data stored in the data buffer 51b and stored in the second input data buffer 51b is stored in the third input data buffer 51c.
[0083]
Then, the start code detection unit 21 detects whether the 3-byte data stored in the first to third input data buffers 51a to 51c matches the start code. The start code detector 21 outputs “1” when the data matches the start code, that is, when the start code is detected, and outputs “0” when the data does not match. “1” and “0” output from the start code detection unit 21 are supplied to the delay circuit 22.
[0084]
In addition, the start code detection unit 21 supplies a position detection signal to the position detection unit 23 every time one byte of data is supplied. The position detection unit 23 increases the numerical value by 1 each time the position detection signal is supplied.
[0085]
Next, the delay circuit 22 supplies a start code detection signal to the detection position holding unit 24 with a delay of m bytes from the timing at which “1” is supplied from the start code detection unit 21.
[0086]
When the start code detection signal is supplied, the detection position holding unit 24 holds the data of the position detection unit 23. The held data is supplied to the data analyzer 4 as a position signal.
[0087]
When the position signal is supplied, the data analyzer 4 starts analyzing the separated data stored in the data buffer 3 and determines whether the packet data of the PES packet is audio encoded data or video encoded data. Is determined.
[0088]
Next, the DMA transfer unit 5 supplies a PES packet whose packet data is audio encoded data to the audio decode buffer 6 in accordance with an instruction from the data analysis unit 4 and converts the PES packet whose packet data is video encoded data. It is supplied to the video decode buffer 7.
[0089]
Then, the audio decode buffer 6 temporarily stores the supplied audio encoded data until the data is read out by the audio decoder, and the video decode buffer 7 stores the supplied video encoded data in the data. The data is temporarily stored until read by the video decoder.
[0090]
As described above, in the PES packet separator 1 to which the present invention is applied, the delay circuit 22 delays the start code detection signal output from the start code detection means 21 by the number of bits of the separated data. Then, when the start code detection signal is supplied, the detection position holding unit 24 holds the data of the position detection unit 23 and supplies the position signal to the data analysis unit 4. The data analyzer 4 starts analyzing the separated data when the position signal is supplied.
[0091]
That is, according to the PES packet separator 1 to which the present invention is applied, the data analyzer 4 detects the timing at which all the separated data is stored in the data buffer 3 without accessing the data buffer 3. It is possible to do.
[0092]
Therefore, in the PES packet separator 1 to which the present invention is applied, it is possible to efficiently analyze the separated data without imposing a load on the CPU 10 provided in the data analyzer 4. For example, even when the separated data is intermittently input to the start code detection unit 2, the analysis of the separated data can be performed without burdening the CPU 10 provided in the data analysis unit 4.
[0093]
In the present embodiment, the case where the present invention is applied to a PES packet separator is described as an example, but the application of the present invention is not limited to the PES packet separator. For example, the present invention may be applied to a separator for separating packet data of a TS (Transport Stream) packet. Further, the present invention may be applied to an audio decoder or a video decoder.
[0094]
【The invention's effect】
In the data analysis system according to the present invention, based on the timing at which the detecting means detects the start code, the timing generating means generates the timing at which all the header data of a predetermined number of bits are stored in the storage means. Then, the analysis unit starts analyzing the header data after the timing generation unit detects the timing at which all data of a predetermined number of bits are stored in the storage unit.
[0095]
That is, in the data analysis system according to the present invention, it is possible for the analysis unit to detect the timing at which the data of a predetermined number of bits following the start code is stored in the storage unit without accessing the storage unit. It becomes possible.
[0096]
Therefore, according to the data analysis system of the present invention, it is possible to efficiently analyze a predetermined number of header data following the start code without putting a load on the analysis means.
[0097]
Further, in the data analysis method according to the present invention, based on the timing at which the start code is detected, after generating the timing at which all header data of a predetermined number of bits following the start code are stored in the storage means, Start analyzing the data.
[0098]
Therefore, according to the data analysis method of the present invention, it is possible to efficiently analyze a predetermined number of header data following the start code.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a format of a PES packet.
FIG. 2 is a schematic diagram showing a PES packet separator to which the present invention is applied.
FIG. 3 is a schematic diagram showing an analysis delay unit in the separator.
FIG. 4 is a schematic diagram showing a start code detection unit in the separator.
FIG. 5 is a schematic diagram showing a delay unit in the separator.
FIG. 6 is a schematic diagram showing a digital multiplex system of the MPEG2-PS system.
FIG. 7 is a schematic diagram showing a conventional PES packet separator.
FIG. 8 is a flowchart showing the operation of the separator.
FIG. 9 is a schematic diagram showing a state where a packet header is intermittently input to a separator.
[Explanation of symbols]
2 Analysis delay unit, 3 data buffer, 4 data detection unit, 21 start code detection device, 22 delay circuit, 23 position detection unit, 24 detection position holding unit

Claims (4)

In a data analysis system that sequentially receives a data stream composed of a plurality of packets and analyzes the data stream,
Detecting means for detecting a start code indicating the beginning of the packet from the input data stream;
Packet data storage means for sequentially storing the data stream;
Timing generation means for generating a timing at which header data of a predetermined number of bits following the start code are all stored in the packet data storage means, based on the timing at which the detection means detects the start code,
Analyzing means for analyzing header data of a predetermined number of bits following the start code among data stored in the packet data storage means,
The data analysis system according to claim 1, wherein the analysis unit starts analyzing header data of a predetermined number of bits following the start code based on the timing generated by the timing generation unit. The detection means supplies a start code detection signal indicating a timing at which a start code is detected to the timing generation means,
The timing generation means includes a delay circuit that operates with a synchronous clock of the data stream, and outputs the start code detection signal with a delay of the predetermined number of bits.
2. The analysis unit according to claim 1, wherein the analysis unit starts analyzing header data of a predetermined number of bits following the start code, based on a timing at which the start code detection signal is output from the timing generation unit. Data analysis system. A program recording means in which a program for analyzing header data of a predetermined number of bits following the start code is recorded,
2. The data analysis method according to claim 1, wherein said analysis means starts said program at a timing when said delay means outputs said start code detection signal, and starts analysis of said predetermined number of bits of header data. system. In a data analysis method for sequentially inputting a data stream composed of a plurality of packets and analyzing the data stream,
A detecting step of detecting a start code indicating the head of the packet from the input data stream;
A storage step of sequentially storing the data stream in storage means;
A timing generation step of generating a timing at which header data of a predetermined number of bits following the start code are all stored in the packet data storage means, based on the timing at which the start code is detected in the detection step;
An analyzing step of analyzing header data of a predetermined number of bits following the start code among data stored in the storage means,
In the analyzing step, a data analyzing method is started, based on a timing at which a start code detection signal is output in the timing generating step, to analyze header data of a predetermined number of bits following the start code.

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