KR960027922A - Parallel processing unit of forward error control for AAL Type 5 service - Google Patents

Parallel processing unit of forward error control for AAL Type 5 service Download PDF

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Publication number
KR960027922A
KR960027922A KR1019940035426A KR19940035426A KR960027922A KR 960027922 A KR960027922 A KR 960027922A KR 1019940035426 A KR1019940035426 A KR 1019940035426A KR 19940035426 A KR19940035426 A KR 19940035426A KR 960027922 A KR960027922 A KR 960027922A
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KR
South Korea
Prior art keywords
crc
syndrome
value
service
forward error
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KR1019940035426A
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Korean (ko)
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KR0128847B1 (en
Inventor
강선
최길영
손승원
최준균
Original Assignee
양승택
재단법인 한국전자통신연구소
조백제
한국전기통신공사
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Priority to KR1019940035426A priority Critical patent/KR0128847B1/en
Publication of KR960027922A publication Critical patent/KR960027922A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H04L2012/5653—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL]
    • H04L2012/5658—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL] using the AAL5

Abstract

본 발명은 AAL 타입 5 서비스 제공시, 채널 에러를 검출하기 위하여 CPCS(Common Part Convergance Sublayer)에서 사용되는 순방향 에러제어 (FEC : Forward Error Correction)로 사용되는 CRC(Cyclic Redundancy Check)-32 바이트 단위의 병렬처리하기 위한 AAL Type 5 서비스를 위한 순방향 에러제어의 병렬처리 장치에 관한 것으로, AAL Type 5 서비스 제공시채널에러를 검출하기 위하여, CPCS에서 순방향 에러제어의 병렬 구현에 관한 것이다. CPCS에서 사용되는 순방향 에러제어는 CRC-32로서, 본 발명을 통하여 송신부에서는 CRC-32를 계산하여 코드 워드를 생성할 때 비트 단위의 직렬 인코더에서에서 바이트 단위의 병렬 인코더로 구현할 수 있고, 수신부에서는 CRC-32를 체크하여 에러를 디코딩할 때 비트 단위의 직렬 디코더에서 바이트 단위의 병렬 디코더로 구현할 수 있다. 또한 이를 이용하여, 다른 임의의 CRC를 계산하여 구현함에있어서 비트단위의 직렬처리에서 바이트나 워드단위 또는 어떤 비트 조합의 단위로 병렬처리 하도록 구현할 수 있다.The present invention provides Cyclic Redundancy Check (CRC) -32 byte units used as Forward Error Correction (FEC) used in Common Part Convergance Sublayer (CPCS) to detect channel errors when providing AAL Type 5 service. The present invention relates to a parallel processing apparatus of forward error control for AAL Type 5 service for parallel processing, and to parallel channel implementation of forward error control in CPCS for detecting channel error in providing AAL Type 5 service. The forward error control used in the CPCS is CRC-32. According to the present invention, when the CRC-32 is calculated by the transmitter to generate a code word, the serial encoder in bits can be implemented as a parallel encoder in bytes. When decoding an error by checking the CRC-32, it can be implemented from a bitwise serial decoder to a bytewise parallel decoder. In addition, by using this, in calculating and implementing any other CRC, it may be implemented to perform parallel processing in units of bytes, words, or any combination of bits in bitwise serial processing.

Description

에이에이엘 타입5(AA Type 5) 서비스를 위한 순방향 에러제어의 병렬처리 장치Parallel Processing Unit of Forward Error Control for AA Type 5 Service

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 CRC-32 인코더 구성도, 제3도는 바이트 단위의 병렬 CRC-32 인코더 구성도, 제4도는 비트 단위의 직렬 CRC-32 디코더 구성도.1 is a configuration diagram of a CRC-32 encoder, FIG. 3 is a configuration diagram of a parallel CRC-32 encoder in units of bytes, and FIG. 4 is a configuration of a serial CRC-32 decoder in units of bits.

Claims (4)

입력데이타와 레지스터의 값을 해당 식을 이용하여 배타적 논리합 연산하는 CRC 생성부(3-1); 상기 CRC 생성부(3-1)로부터의 출력값을 저장하기 위한 레지스터부(3-2); 상기 CRC 생성부(3-1) 및 레지스터부(3-2)에 연결되어 코드워드를 생성하기 위하여 입력데이타와 계산된 CRC를 다중화하기 위한 다중화부(3-3); 및 상기 CRC 생성부(3-1)와 레지스터부(3-2) 및 다중화부(3-3)를 제어하는 제어신호를 생성하는 제어신호 생성부(3-4)를 구비하여 바이트 단위의 병렬CRC-32 인코딩을 수행하도록 한 것을 특징으로 하는 AAL 타입5 서비스를 위한 순방향 에러제어의 병렬처리 장치.A CRC generation unit 3-1 for performing an exclusive OR operation on the input data and the value of the register using the corresponding equation; A register section 3-2 for storing an output value from the CRC generation section 3-1; A multiplexer (3-3) connected to the CRC generator (3-1) and the register unit (3-2) for multiplexing the input data and the calculated CRC to generate a codeword; And a control signal generator 3-4 for generating a control signal for controlling the CRC generator 3-1, the register unit 3-2, and the multiplexer 3-3. A parallel processing unit of forward error control for AAL type 5 service, characterized by performing CRC-32 encoding. 제1항에 있어서, 바이트 단위로 입력되는 데이타의 값에 따라 변하는 CRC 값의 갱신을 위하여 상기 레지스터부(3-2)에서 상기 CRC 생성부(3-1)로 입력되는 CRC 값 32비트를 한 번에 보내도록 구성한 것을 특징으로 하는 AAL 타입5서비스를 위한 순방향 에러제어의 병렬처리 장치.The CRC value 32 bits inputted from the register section 3-2 to the CRC generation section 3-1 is used for updating a CRC value that changes according to the data value input in byte units. A parallel processing unit of forward error control for AAL type 5 service, characterized in that configured to send at one time. 수신데이타를 입력받아 배타적 논리합 연산에 의한 신드롬을 생성하는 신드롬 생성부(5-1); 상기 신드롬 생성부(5-1에서 생성된 임시적인 신드롬값을 저장하고 이를 갱신하기 위하여 상기 신드롬 생성부(5-1)에 이 신드롬값을비트 단위로 보내는 레지스터부(5-2); 상기 레지스터부(5-2)에 연결되어 계산된 신드롬 값과 비교하여 수신데이타의 에러발생 여부를 알려주는 상태 신호를 출력하는 신드롬 비교부(4-3); 상기 신드롬 비교부(4-3)에 연결되어 수신 데이타의 상태 신호를 입력받아 버퍼를 삭제 또는 데이타를 전송하며, 전체 수신데이타에 대한 신드롬을 계산하는 동안 수신데이타를저장하는 수신버퍼부(5-5); 및 상기 신드롬 생성부(5-1)와 레지스터부(5-2), 및 신드롬 비교부(5-3)와 수신버퍼부(5-5)로각각의 제어 신호를 생성하여 제공하는 제어 신호 생성부(5-4)를 구비하여 바이트 단위의 병렬 CRC-32 디코딩을 수행하도록 구성한 것을 특징으로 하는 AAL 타입 5 서비스를 위한 순방향 에러제어의 병렬처리 장치.A syndrome generator 5-1 receiving the received data and generating a syndrome by an exclusive-OR operation; A register unit 5-2 for sending the syndrome value in units of bits to the syndrome generator 5-1 in order to store and update the temporary syndrome value generated by the syndrome generator 5-1; A syndrome comparison unit 4-3 for outputting a status signal indicating whether an error of received data is generated by comparing with the calculated syndrome value connected to the unit 5-2, and connected to the syndrome comparison unit 4-3; Receiving a status signal of the received data, deleting the buffer or transmitting the data, and receiving a buffer 5-5 for storing the received data while calculating the syndrome for the entire received data; 1) and a register section 5-2, and a control signal generation section 5-4 for generating and providing respective control signals to the syndrome comparing section 5-3 and the receiving buffer section 5-5. To perform parallel CRC-32 decoding on a byte basis. Parallel processing unit of forward error control for AAL type 5 service. 제3항에 있어서, 바이트 단위로 입력되는 데이타의 값에 따라 변하는 신드롬 값의 생성을 위하여, 상기 레지스터부(5-2)에서 상기 신드롬 생성부(5-1)로 입력되는 신드롬 값 32비트를 한 번에 보내도록 구성한 것을 특징으로하는 AAL 타입 5 서비스를 위한 순방향 에러제어의 병렬처리 장치.The method according to claim 3, wherein a 32-bit syndrome value input from the register section 5-2 to the syndrome generator section 5-1 is generated in order to generate a syndrome value which varies according to the value of data input in byte units. A parallel processing unit of forward error control for AAL type 5 service, characterized in that configured to send at one time. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940035426A 1994-12-20 1994-12-20 Aa-type 5-service system KR0128847B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100268125B1 (en) * 1997-12-03 2000-10-16 이계철 The circuit of parallel crc generator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100268125B1 (en) * 1997-12-03 2000-10-16 이계철 The circuit of parallel crc generator

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