KR960026752A - Manufacturing method of complementary transistor (CMOSFET) of fine line width - Google Patents

Manufacturing method of complementary transistor (CMOSFET) of fine line width Download PDF

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KR960026752A
KR960026752A KR1019940034048A KR19940034048A KR960026752A KR 960026752 A KR960026752 A KR 960026752A KR 1019940034048 A KR1019940034048 A KR 1019940034048A KR 19940034048 A KR19940034048 A KR 19940034048A KR 960026752 A KR960026752 A KR 960026752A
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mos region
ion implantation
sidewalls
manufacturing
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KR1019940034048A
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KR100356784B1 (en
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황준
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

미세선폭의 상보형 트랜지스터(CMOSFET)를 제조하는 방법.A method of manufacturing a complementary transistor (CMOSFET) having a fine line width.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

반도체 소자의 고입집적시 주로 발생하는 문제점인 짧은 채널로 인해 펀치-드루우에 취액해지는 현상과 드레인 전류가 감소하는 형상을 얕은 소오스/드레인 접합없이 해결하고자 함.In order to solve the phenomenon that the short drain channel, which is a problem that occurs mainly in high integration of semiconductor devices, is absorbed by the punch-draw and the shape in which the drain current is reduced, without shallow source / drain junctions.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

CMOSFET 소자에서 N-MOS 지역과 P-MOS 지역의 게이트 전극의 양측벽에 형성되는 측벽 스페이서 크기를 각각 다르게 하여 드레인 전류의 감소를 방지하고, 펀치-드루우 문제를 효율적으로 방지하면서 미세 선폭을 가진 CMOSFET 소자를 제조하고자 함.By varying the size of the sidewall spacers formed on both sidewalls of the gate electrodes of the N-MOS region and the P-MOS region in the CMOSFET device, it is possible to reduce the drain current and to effectively prevent the punch-drow problem, To manufacture CMOSFET device.

4. 발명의 중요한 용도4. Important uses of the invention

미세 선폭의 고집적 반도체 소자 제조에 이용됨.It is used to manufacture highly integrated semiconductor devices with fine line width.

Description

미세선폭의 상보형 트랜지스터(CMOSFET) 제조 방법Manufacturing method of complementary transistor (CMOSFET) of fine line width

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1F는 본 발명의 한 실시예에 따른 미세 선폭의 CMOSFET 제조 방법의 제조 공정을 도시하는 도면.1A to 1F illustrate a manufacturing process of a method for fabricating a CMOSFET having a fine line width according to an embodiment of the present invention.

Claims (5)

미세선폭의 상보형 트랜지스터(CMOSFET)를 제조하는 방법에 있어서, 반도체 기판상의 N-MOS 지역과 P-MOS 지역 각각에 게이트 전극을 형성하고, 각각 저도핑 이온 주입을 실시하는 단계와, 전체 구조 상부에 스페이서 산화막을 증착하는 단계와, 상기 N-MOS 지역과 P-MOS 지역중 어느 한 지역에 제1포토레지스트 마스크 패턴을 형성한 다음 상기 스페이서 산화막을 식각하여 제1게이트 전극 양측벽에 소정 두께의 제1측벽 스페이서를 형성하고, 소오스/드레인 영역을 형성하기 위한 이온 주입을 실시하는 단계 및, 상기 제1포토레지스터 마스트 패턴을 제거하고, 상기 N-MOS 지역과 P-MOS 지역중 다른 지역에 제2포토레지스트 마스트 패턴을 형성한 다음 상기 스페이서 산화막을 식각하여 제2게이트 전극 양측벽에 상기 제1측벽 스페이서와 다른 두께의 제2측벽 스페이서를 형성하고, 소오스/드레인 영역을 형성하기 위한 이온 주입을 실시하는 단계를 포함해서 이루어진 미세선폭의 상보형 트랜지스터 제조 방법.A method of manufacturing a complementary transistor (CMOSFET) having a fine line width, comprising: forming a gate electrode in each of an N-MOS region and a P-MOS region on a semiconductor substrate, and performing low doping ion implantation, respectively, Depositing a spacer oxide layer on the spacer layer, forming a first photoresist mask pattern in one of the N-MOS region and the P-MOS region, and then etching the spacer oxide layer to a predetermined thickness on both sidewalls of the first gate electrode. Forming a first sidewall spacer, performing ion implantation to form a source / drain region, removing the first photoresist mast pattern, and removing the first photoresist mast pattern in another region of the N-MOS region and the P-MOS region A second photoresist mask pattern is formed, and then the spacer oxide layer is etched to form second photoresist spacers having a thickness different from that of the first sidewall spacers on both sidewalls of the second gate electrode. And forming a source / drain region, and performing ion implantation to form a source / drain region. 제1항에 있어서, 상기 N-MOS 지역에 저도핑 이온 주입을 실시한 후, 펀치-드루우 스톱 영역을 형성하기 위한 포켓 이온을 주입하는 단계를 더 포함하는 것을 특징으로 하는 미세선폭의 상보형 트랜지스터 제조 방법.The complementary transistor of claim 1, further comprising: implanting pocket ions for forming a punch-draw stop region after performing low doping ion implantation into the N-MOS region. Manufacturing method. 제2항에 있어서, 상기 포켓 이온 주입 단계는 좌, 우측 각각 약 30도의 경사를 주어 BF2이온을 순차적으로 주입하는 것을 특징으로 하는 미세 선폭의 상보형 트랜지스터 제조 방법.3. The method of claim 2, wherein the pocket ion implantation step injects BF 2 ions sequentially by giving an inclination of about 30 degrees to the left and the right sides, respectively. 제1항 또는 제2항에 있어서, 상기 모든 이온 주입 단계를 완료한 다음에 어닐링 처리를 수행하는 것을 특징으로 하는 미세선폭의 상보형 트랜지스터 제조 방법.3. The method of claim 1 or 2, wherein the annealing treatment is performed after all the ion implantation steps are completed. 제1항, 2항 또는 제3항에 있어서, 상기 N-MOS 지역의 게이트 전극 양측벽에 형성되는 측벽 스페이서의 두께는 약 0.15㎛이고, 상기 P-MOS 지역의 게이트 전극 양측벽에 형성되는 측벽 스페이서의 두께는 약 0.25㎛인 것을 특징으로 하는 미세선폭의 상보형 트랜지스터 제조 방법.4. The sidewall spacers of claim 1, 2 or 3, wherein the sidewall spacers formed on both sidewalls of the gate electrode in the N-MOS region have a thickness of about 0.15 mu m, and the sidewalls formed on both sidewalls of the gate electrode in the P-MOS region. A method of manufacturing a complementary transistor having a fine line width, wherein the spacer has a thickness of about 0.25 μm. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940034048A 1994-12-14 1994-12-14 Method for manufacturing cmos fet having micro line width KR100356784B1 (en)

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JP2559397B2 (en) * 1987-03-16 1996-12-04 株式会社日立製作所 Semiconductor integrated circuit device and manufacturing method thereof
JPH0493063A (en) * 1990-08-09 1992-03-25 Nec Corp Manufacture of semiconductor device
JPH06151742A (en) * 1992-11-02 1994-05-31 Mitsubishi Electric Corp Semiconductor device and manufacture thereof

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