KR960026673A - Integrated structure of chip and mounting method - Google Patents

Integrated structure of chip and mounting method Download PDF

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Publication number
KR960026673A
KR960026673A KR1019940038302A KR19940038302A KR960026673A KR 960026673 A KR960026673 A KR 960026673A KR 1019940038302 A KR1019940038302 A KR 1019940038302A KR 19940038302 A KR19940038302 A KR 19940038302A KR 960026673 A KR960026673 A KR 960026673A
Authority
KR
South Korea
Prior art keywords
electrode
integrated circuit
circuit chip
conductive paste
base
Prior art date
Application number
KR1019940038302A
Other languages
Korean (ko)
Inventor
박진우
Original Assignee
윤종용
삼성전관 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 윤종용, 삼성전관 주식회사 filed Critical 윤종용
Priority to KR1019940038302A priority Critical patent/KR960026673A/en
Priority to JP7159386A priority patent/JPH08186150A/en
Publication of KR960026673A publication Critical patent/KR960026673A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

인접하는 전극간에 전기적 쇼츠를 방지할 수 있는 집적회로 칩 구조체 및 그 실장방법에 대해 개시한다. 이는 제1전극(31)이 형성된 집적회로 칩(30)과, 이 제1전극(31)에 대응하여 제2전극(41)이 형성된 베이스(40)를 접합할시에, 제1전극(31)과 제2전극(41)의 상호 대향면에만 도전성 페이스트(50)를 도포하여 접합시킨 구조를 가진다.An integrated circuit chip structure capable of preventing electrical shorts between adjacent electrodes and a mounting method thereof are disclosed. This is because when the integrated circuit chip 30 having the first electrode 31 formed thereon and the base 40 on which the second electrode 41 is formed corresponding to the first electrode 31 are joined, the first electrode 31 is formed. ) And the second electrode 41 have a structure in which the conductive paste 50 is applied and bonded only to the mutually opposite surfaces.

Description

집적회로 칩의 실장 구조체 및 그 실장방법Integrated structure of chip and mounting method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 집적회로 칩의 실장 구조체를 나타낸 단면도, 제3도는 본 발명에 따른 집적회로 칩의 실장방법을 나타낸 공정도, 제4도 및 제5도는 본 발명에 따른 실장 구조체의 적용예를 나타낸 개략도이다.2 is a cross-sectional view showing a mounting structure of an integrated circuit chip according to the present invention, FIG. 3 is a process diagram showing a method of mounting an integrated circuit chip according to the present invention, and FIGS. 4 and 5 are application of the mounting structure according to the present invention. A schematic diagram showing an example.

Claims (6)

소정패턴의 제1전극이 형성된 집적회로 칩과 제1전극에 대응하여 제2전극이 형성된 베이스가 소정의 접합수단에 의하여 접착된 집적회로 칩 구조체에 있어서, 상기 접합수단은 상기 제1전극과 제2전극의 상호 대향면에만 도전성 페이스트를 개재하여서 접합시키는 것을 특징으로 하는 집적회로 칩 구조체.An integrated circuit chip structure in which an integrated circuit chip on which a first electrode of a predetermined pattern is formed and a base on which a second electrode is formed corresponding to a first electrode are bonded by a predetermined bonding means, wherein the bonding means comprises the first electrode and the first electrode. An integrated circuit chip structure, comprising: bonding a conductive paste only on opposing surfaces of two electrodes. 제1항에 있어서, 상기 도전성 페이스트는 도전성 폴리머인 것을 특징으로 하는 집적회로 칩 구조체.The integrated circuit chip structure of claim 1, wherein the conductive paste is a conductive polymer. 소정패턴의 제1전극과 이 제1전극의 상면에 범프가 형성된 집적회로 칩과, 제1전극에 대응하여 제2전극이 형성된 베이스가 소정의 접합수단에 의하여 접착된 집적회로 칩 구조체에 있어서, 상기 접합수단은 상기 범프를 도전성 페이스트로 형성하여서 접합시키는 것을 특징으로 하는 집적회로 칩 구조체.An integrated circuit chip structure in which a first electrode of a predetermined pattern, an integrated circuit chip having bumps formed on an upper surface of the first electrode, and a base on which a second electrode is formed corresponding to the first electrode are bonded by predetermined bonding means, And the joining means is formed by joining the bumps with a conductive paste. 제3항에 있어서, 상기 도전성 페이스트는 도전성 폴리머인 것을 특징으로 하는 집적회로 칩 구조체.4. The integrated circuit chip structure of claim 3, wherein the conductive paste is a conductive polymer. 제1전극이 형성된 집적회로 칩을 제2전극이 형성된 베이스에 접합시키는 집적회로 칩 실장방법에 있어서, 상기 제2전극이 형성된 베이스 포토 레지스터를 도포하는 단계와, 상기 포토 레지스터를 상기 제2전극의 상면에 노출되도록 노광하는 단계와, 상기 제2전극의 상면에 도전성 페이스트를 도포하는 단계와, 상기 포토 레지스터를 제거시키는 단계와, 상기 제1전극을 상기 도전성 페이스트에 접착시켜서 집적회로 칩을 베이스에 실장하는 단계를 포함하여 되는 것을 특징으로 하는 집적회로 칩 실정방법.An integrated circuit chip mounting method for bonding an integrated circuit chip having a first electrode to a base having a second electrode, the method comprising: applying a base photo resistor on which the second electrode is formed; Exposing the integrated circuit chip to a base by exposing to an upper surface, applying a conductive paste to the upper surface of the second electrode, removing the photoresist, and adhering the first electrode to the conductive paste. Integrated circuit chip actual method comprising the step of mounting. 제5항에 있어서, 상기 도전성 페이스트는 도전성 폴리머를 사용하는 것을 특징으로 하는 집적회로 칩 실장방법.6. The integrated circuit chip mounting method according to claim 5, wherein the conductive paste uses a conductive polymer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940038302A 1994-12-28 1994-12-28 Integrated structure of chip and mounting method KR960026673A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019940038302A KR960026673A (en) 1994-12-28 1994-12-28 Integrated structure of chip and mounting method
JP7159386A JPH08186150A (en) 1994-12-28 1995-06-26 Mounting structure body of integrated circuit chip and its mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940038302A KR960026673A (en) 1994-12-28 1994-12-28 Integrated structure of chip and mounting method

Publications (1)

Publication Number Publication Date
KR960026673A true KR960026673A (en) 1996-07-22

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940038302A KR960026673A (en) 1994-12-28 1994-12-28 Integrated structure of chip and mounting method

Country Status (2)

Country Link
JP (1) JPH08186150A (en)
KR (1) KR960026673A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6114088A (en) * 1999-01-15 2000-09-05 3M Innovative Properties Company Thermal transfer element for forming multilayer devices

Also Published As

Publication number Publication date
JPH08186150A (en) 1996-07-16

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