KR960026151A - Thin junction formation method of semiconductor device - Google Patents

Thin junction formation method of semiconductor device Download PDF

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KR960026151A
KR960026151A KR1019940040681A KR19940040681A KR960026151A KR 960026151 A KR960026151 A KR 960026151A KR 1019940040681 A KR1019940040681 A KR 1019940040681A KR 19940040681 A KR19940040681 A KR 19940040681A KR 960026151 A KR960026151 A KR 960026151A
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South Korea
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silicon
impurities
substrate
silicon layer
oxide film
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KR1019940040681A
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KR0161384B1 (en
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박정우
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

높은 소오스/드레인 구조(Elevated Source/Drain:ESD)를 가지는 트랜지스터에 있어서 기판에 실리콘층을 증착하는 방법을 개시한다. 높은 소오스/드레인 구조의 실리콘층의 형성방법은, 반도체기판에 산화막과 플라즈마-산화막을 연속적으로 도포하고 소정부분을 식각하여 소오스/드레인영역에 해당하는 기판을 노출시키는 단계와, 기판전면에 질화실리콘막을 도포한 뒤 이방성식각을 하여 상기 산화막과 플라즈마-산화막의 측벽에 스페이서를 형성하는 단계와, 실리콘을 함유하는 화합물을 가스분위기에서 엑시머레이저를 기판전면에 가하여 상기 노출된 기판에만 실리콘층을 증착하는 단계와, 불순물을 함유한 화합물 가스분위기에서 레이저를 기판전면에 가하여 상기 실리콘층 불순물을 도핑함과 동시에 상기 불순물을 활성화시키는 단계로 구성된다. 또한 상기의 실리콘 적층단계와 불순물의 도핑과 활성화단계를 반복하여 원하는 높이의 실리콘층을 성장시킨다.A method of depositing a silicon layer on a substrate in a transistor having a high source / drain (ESD) structure is disclosed. A method of forming a high source / drain structure silicon layer includes applying an oxide film and a plasma-oxide film to a semiconductor substrate successively, etching a predetermined portion to expose a substrate corresponding to the source / drain region, and silicon nitride on the entire surface of the substrate. Forming a spacer on the sidewalls of the oxide film and the plasma-oxide film by applying an anisotropic etch to the film, and depositing a silicon layer only on the exposed substrate by applying a compound containing silicon to the entire surface of the substrate in a gas atmosphere. And a step of activating the impurities while simultaneously doping the silicon layer impurities by applying a laser to the front surface of the substrate in a compound gas atmosphere containing impurities. In addition, the silicon lamination step and the doping and activating steps of the impurities are repeated to grow a silicon layer having a desired height.

이에 따라 높은 소오스/드레인구조의 실리콘에피택시층을 간단한 공정으로 성장시킬 수 있으며 고집적반도체 메모리장치에 적합한 소오스/드레인의 얇은 접합을 형성할 수 있다.Accordingly, the silicon epitaxy layer having a high source / drain structure can be grown in a simple process, and a thin junction of source / drain suitable for a highly integrated semiconductor memory device can be formed.

Description

반도체장치의 얇은 접합형성방법Thin junction formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2F도는 본 발명에 따라 트랜지스터의 실리콘층을 성장시키는 제조방법을 나타낸 단면도이다.2A to 2F are cross-sectional views showing a manufacturing method for growing a silicon layer of a transistor according to the present invention.

Claims (6)

반도체기판의 소자분리영역과 활성영역으로 나누어지는 반도체장치에 있어서, 반도체기판 전면에 반응차단막을 도포하는 단계; 상기 반응차단막의 소정 부분을 패터닝하여 소오스/드레인영역에 해당하는 상기 활성영역의 일부분을 노출시키는 단계; 실리콘을 함유하는 화합물 가스분위기에서 레이저를 가하여 상기 노출된 부분에만 실리콘층을 증착시키는 단계; 상기 레이저를 이용하여 상기 실리콘층 하부에 불순물을 도핑함과 동시에 활성화시키는 단계; 및 상기 실리콘증착단계 및 불순물의 도핑과 활성화단계를 반복하여 상기 실리콘증착단계 및 불순물의 도핑과 활성화단계를 반복하여 상기 실리콘층을 소정 두께로 성장시키는 단계를 구비함을 특징으로 하는 반도체장치의 제조방법.A semiconductor device divided into a device isolation region and an active region of a semiconductor substrate, comprising: applying a reaction barrier film over an entire surface of the semiconductor substrate; Patterning a predetermined portion of the reaction blocking membrane to expose a portion of the active region corresponding to a source / drain region; Applying a laser in a compound gas atmosphere containing silicon to deposit a silicon layer only on the exposed portion; Activating at the same time as doping impurities under the silicon layer using the laser; And growing the silicon layer to a predetermined thickness by repeating the silicon deposition step and the doping and activating step of the impurity, and repeating the silicon deposition step and the doping and activating step of the impurity. Way. 제1항에 있어서, 상기 실리콘을 함유하는 화합물이 SiH4, SiHCL2,SiH2CL2, 및 SCL4중에서 선택된 어느 하나임을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the silicon-containing compound is any one selected from SiH 4 , SiHCL 2 , SiH 2 CL 2 , and SCL 4 . 제1항에 있어서, 상기 불순물이 도핑과 활성화단계는 불순물을 함유하는 화합물 가스 분위기에서 실시됨을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the doping and activating the impurities are performed in a compound gas atmosphere containing the impurities. 제1항에 있어서, 상기 레이저가 엑시머레이저임을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein said laser is an excimer laser. 제1항에 있어서, 상기 반응차단막이 각각 패드산화막과 플라즈마-산화막임을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein said reaction blocking film is a pad oxide film and a plasma oxide film, respectively. 제3항에 있어서, 상기 불순물을 함유하는 화합물이 B2H6또는 PH3임을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 3, wherein the compound containing impurities is B 2 H 6 or PH 3 . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940040681A 1994-12-31 1994-12-31 Method of manufacturing semiconductor for shallow junction KR0161384B1 (en)

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KR1019940040681A KR0161384B1 (en) 1994-12-31 1994-12-31 Method of manufacturing semiconductor for shallow junction

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KR1019940040681A KR0161384B1 (en) 1994-12-31 1994-12-31 Method of manufacturing semiconductor for shallow junction

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KR960026151A true KR960026151A (en) 1996-07-22
KR0161384B1 KR0161384B1 (en) 1999-02-01

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