KR960025023A - Multiplexing System - Google Patents

Multiplexing System Download PDF

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Publication number
KR960025023A
KR960025023A KR1019940036736A KR19940036736A KR960025023A KR 960025023 A KR960025023 A KR 960025023A KR 1019940036736 A KR1019940036736 A KR 1019940036736A KR 19940036736 A KR19940036736 A KR 19940036736A KR 960025023 A KR960025023 A KR 960025023A
Authority
KR
South Korea
Prior art keywords
cpu
multiplexing system
watchdog timer
circuit
wdt
Prior art date
Application number
KR1019940036736A
Other languages
Korean (ko)
Inventor
홍석영
Original Assignee
한승준
기아자동차 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 한승준, 기아자동차 주식회사 filed Critical 한승준
Priority to KR1019940036736A priority Critical patent/KR960025023A/en
Publication of KR960025023A publication Critical patent/KR960025023A/en

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Abstract

본 발명은 다중화 시스템에 관한 것으로서, 진단IC(3)에 구비된 다른 극성을 가진 워치도그타이머(4,5:WDT)를 CPU(1)(2)에 의해 프로그램동작 신호(6)(7)를 입력하고 CPU(1)(2)에 리셋트(8)(9) 신호를 출력하며 CPU(2)(2)에는 고장표시회로(13)와 회로절환장치(12)을 연결하여 워치도그타이머(4)(5)의 출력이 동시에 모드에서 고장발생시 시스템의 정지를 방지한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexing system, wherein a watchdog timer (4, 5: WDT) having different polarities included in a diagnostic IC (3) is programmed by a CPU (1) (2) and a program operation signal (6) (7). And reset (8) and (9) signals to the CPU (1) and (2) .The watchdog timer is connected to the CPU (2) and the fault display circuit (13) and the circuit changer (12). The outputs of (4) and (5) prevent the system from stopping in the event of a failure at the same time.

Description

다중화 시스템(System)Multiplexing System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 구성 회로도.1 is a configuration circuit diagram of the present invention.

Claims (1)

진단IC(3)에 구비되 다른 극성을 가진 워치도그타이머(4,5:WDT)를 CPU(1)(2)에 의해 프로그램동작 신호(6)(7)를 입력하고 CPU(1)(2)에 리셋트(8)(9) 신호를 출력하며, CPU(2)(2)에는 고장표시회로(13)와 회로절환장치(12)을 연결하여 워치도그타이머(4)(5)의 출력이 동시에 모드에서 고장발생시 시스템의 정지를 방지한 것을 특징으로 하는 다중화 시스템.The watchdog timers 4,5: WDT having different polarities included in the diagnostic IC 3 are inputted by the CPU 1 and 2 to input the program operation signals 6 and 7 to the CPU 1 and 2, respectively. Outputs the watchdog timer (4) and (5) to the CPU (2) (2) by connecting the fault display circuit (13) and the circuit changer (12). At the same time, the multiplexing system characterized in that the system stops when a failure occurs in the mode. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940036736A 1994-12-26 1994-12-26 Multiplexing System KR960025023A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940036736A KR960025023A (en) 1994-12-26 1994-12-26 Multiplexing System

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940036736A KR960025023A (en) 1994-12-26 1994-12-26 Multiplexing System

Publications (1)

Publication Number Publication Date
KR960025023A true KR960025023A (en) 1996-07-20

Family

ID=66769567

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940036736A KR960025023A (en) 1994-12-26 1994-12-26 Multiplexing System

Country Status (1)

Country Link
KR (1) KR960025023A (en)

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