KR960024950A - Cyclic redundancy test code generation circuit - Google Patents

Cyclic redundancy test code generation circuit Download PDF

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Publication number
KR960024950A
KR960024950A KR1019940040804A KR19940040804A KR960024950A KR 960024950 A KR960024950 A KR 960024950A KR 1019940040804 A KR1019940040804 A KR 1019940040804A KR 19940040804 A KR19940040804 A KR 19940040804A KR 960024950 A KR960024950 A KR 960024950A
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South Korea
Prior art keywords
output
cyclic redundancy
check code
exclusive
redundancy check
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KR1019940040804A
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Korean (ko)
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KR100285425B1 (en
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박용우
박정일
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김광호
삼성전자 주식회사
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Priority to KR1019940040804A priority Critical patent/KR100285425B1/en
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Publication of KR100285425B1 publication Critical patent/KR100285425B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

데이타 전송시 에러를 검출하기 위한 순환중복검사(Cyclic Redunacy Check)코드를 발생하는 회로에 관한 것이다.The present invention relates to a circuit for generating a Cyclic Redunacy Check code for detecting an error in data transmission.

2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention

순환중복검사코드 발생회로에 있어서 순환중복검사코드를 발생할 때 처리속도를 높이기 위해서 보다 고속으로 동작 가능한 구성 부품들을 사용하여야만 하는 것을 개선한다.In the cyclic redundancy check code generation circuit, it is improved to use components that can be operated at higher speed in order to increase the processing speed when generating the cyclic redundancy check code.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

메세지 데이타의 우수번째 비트들과 기수번째 비트들을 순차로 1비트씩 입력하여 동시에 2비트를 각각 순환적으로 쉬프트시켜 우수번째 비트와 기수번째 비트의 순환중복검사코드를 동시에 생성한다.The most significant bits and the odd bits of the message data are sequentially inputted one bit at a time, and two bits are cyclically shifted at the same time to generate a cyclic redundancy check code of the even and odd bits.

4. 발명의 중용한 용도4. Significant use of the invention

고속으로 데이타를 전송하는데 이용된다.It is used to transfer data at high speed.

Description

순환중복검사코드 발생회로Cyclic redundancy test code generation circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 CRC코드 발생회로도.2 is a CRC code generation circuit diagram according to the present invention.

Claims (2)

메세지 데이타에 대한 순환중복검사코드를 발생하는 회로에 있어서, 상기 메세지 데이타의 우수번째 비트들을 1비트씩 순차로 입력하여 순환적으로 쉬프트시켜 우수번째 비트의 순환중복검사코드를 생성하는 제1순환중복검사코드 발생수단과, 상기 메세지 데이타의 기수번째 비트들을 1비트씩 순차로 입력하여 순환적으로 쉬프트시켜 기수번째 비트의 순환중복검사코드를 생성하는 제2순환중복검사코드를 발생수단으로 구성하는 것을 특징으로 하는 순환중복검사코드 발생회로.In a circuit for generating a cyclic redundancy check code for message data, a first cyclic redundancy for generating a cyclic redundancy check code of even-numbered bits by sequentially inputting even-numbered bits of the message data sequentially by one bit Generating means and a second cyclic redundancy check code for generating a cyclic redundancy check code of the odd bit by sequentially inputting the odd bits of the message data one bit at a time. Cyclic redundancy test code generation circuit characterized in. 생성다항식 CRC-CCITT을 사용하여 메세지 데이타에 대한 순환중복검사코드를 발생하는 회로에 있어서, 서로 순환적으로 접속되어 상기 메세지 데이타의 우수번째 비트들을 소정클럭신호에 의해 순차적으로 1비트씩 쉬프트시켜 순환중복검사코드의 각 우수번째 비트를 출력하는 제1~제8래치회로(50~64)와, 서로 순환적으로 접속되어 상기 메세지 데이타의 기수번째 비트들을 클럭신호에 의해 순차적으로 1비트씩 쉬프트시켜 순환중복검사코드의 각 기수번째 비트를 출력하는 제9~제16래치회로(66~80)와, 상기 제8래치회로(64)의 출력단자의 출력과 상기 메세지 데이타의 우수번째 비트를 배타적 논리합하는 배타적 논리합게이트(86)와, 상기 제3, 제4래치회로(54,56)의 사이에 접속되어 상기 제3래치회로(54)의 출력단자의 출력과 배타적 논리합게이트(86)의 출력을 배타적 논리합하여 제4래치회로(56)의 입력단자에 인가하는 배타적 논리합게이트(82)와 상기 제6, 제7래치회로(60,62)의 사이에 접속되어 상기 제6래치회로(60)의 출력단자의 출력과 배타적 논리합게이트(86)의 출력을 배타적 논리합하여 상기 제7래치회로(62)의 입력단자에 인가하는 배타적 논리합게이트(84)와, 상기 제16래치회로(80)의 출력단자의 출력과 상기 메세지 데이타의 기수번째 비트를 배타적 논리합하는 배타적 논리합게이트(92)와, 상기 제10, 제11래치회로(68,70)의 사이에 접속되어 상기 제10래치회로(68)의 출력단자의 출력과 배타적 논리합게이트(92)의 출력을 배타적 논리합하여 상기 제11래치회로(70)의 입력단자에 인가하는 배타적 논리합게이트(88)와, 상기 제14, 제15래치회로(76,78)의 사이에 접속되어 상기 제14래치회로(76)의 출력단자의 출력과 배타적 논리합게이트(92)의 출력을 배타적 논리합하여 상기 제15래치회로(78)의 입력단자에 인가하는 배타적 논리합게이트(90)로 구성하는 것을 특징으로 하는 순환중복검사코드 발생회로.A circuit for generating a cyclic redundancy check code for message data using a polynomial CRC-CCITT, wherein the circuit is cyclically connected to each other to shift the even-numbered bits of the message data sequentially by one bit by a predetermined clock signal. The first to eighth latch circuits 50 to 64 outputting each even bit of the redundancy check code are cyclically connected to each other to shift the odd-numbered bits of the message data sequentially one bit by a clock signal. The exclusive logical sum of the ninth to sixteenth latch circuits 66 to 80 outputting each odd bit of the cyclic redundancy check code, the output of the eighth latch circuit 64, and the even-most bit of the message data Is connected between the exclusive logical sum gate 86 and the third and fourth latch circuits 54 and 56 to output the output of the output terminal of the third latch circuit 54 and the output of the exclusive logical sum gate 86.The exclusive logic sum gate 82 applied to the input terminal of the fourth latch circuit 56 and the sixth and seventh latch circuits 60 and 62 by an exclusive logic sum is connected to the sixth latch circuit 60. An exclusive logic sum gate 84 which applies an exclusive logic sum of the output of the output terminal and the output of the exclusive logic sum gate 86 to the input terminal of the seventh latch circuit 62, and the output terminal of the sixteenth latch circuit 80. Is connected between an exclusive logical sum gate 92 for exclusive OR of the output of the message data and the odd bit of the message data, and the output of the tenth latch circuit 68 by being connected between the tenth and eleventh latch circuits 68 and 70. An exclusive logic sum gate 88 for applying an exclusive logic sum of the output of the terminal and the output of the exclusive logic sum gate 92 to the input terminal of the eleventh latch circuit 70, and the fourteenth and fifteenth latch circuits 76 and 78. Is connected between the output terminal and the output terminal of the fourteenth latch circuit 76 To exclusive-OR the output of the OR gate 92, a cyclic redundancy check code generating circuit characterized in that consists of exclusive-OR gate 90 is applied to the input terminal of the first latch circuit 15 (78). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940040804A 1994-12-31 1994-12-31 Generating circuit for cyclic redundancy check code KR100285425B1 (en)

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KR1019940040804A KR100285425B1 (en) 1994-12-31 1994-12-31 Generating circuit for cyclic redundancy check code

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Application Number Priority Date Filing Date Title
KR1019940040804A KR100285425B1 (en) 1994-12-31 1994-12-31 Generating circuit for cyclic redundancy check code

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KR960024950A true KR960024950A (en) 1996-07-20
KR100285425B1 KR100285425B1 (en) 2001-04-02

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KR930024307A (en) * 1992-05-27 1993-12-22 정용문 Circuit for detecting cyclic loop code

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