KR960018824A - Internal voltage generation circuit capable of detecting external voltage at burn-in - Google Patents

Internal voltage generation circuit capable of detecting external voltage at burn-in Download PDF

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Publication number
KR960018824A
KR960018824A KR1019940029940A KR19940029940A KR960018824A KR 960018824 A KR960018824 A KR 960018824A KR 1019940029940 A KR1019940029940 A KR 1019940029940A KR 19940029940 A KR19940029940 A KR 19940029940A KR 960018824 A KR960018824 A KR 960018824A
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South Korea
Prior art keywords
voltage
burn
reference voltage
pmos transistor
output
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KR1019940029940A
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Korean (ko)
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KR0121146B1 (en
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김삼수
김영현
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문정환
금성일렉트론 주식회사
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Priority to KR1019940029940A priority Critical patent/KR0121146B1/en
Publication of KR960018824A publication Critical patent/KR960018824A/en
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Publication of KR0121146B1 publication Critical patent/KR0121146B1/en

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    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is dc
    • G05F3/10Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

본 발명은 번-인시 외부전압 감지가 가능한 내부전압 발생회로에 관한 것으로, 종래에는 번-인(Burn-in) 실험조건이 칩 동작시로 한정되며, 엔트리(Entry)와 엑사이트(Exit)에 대한 히스테리시스가 고려되어 있지않기 때문에 번-인모드로 들어갈때 오실레이션 현상이 일어나는 문제점이 있다. 따라서 본 발명은 내부전압 발생회로에서 증가하는 외부전압이 일정구간을 초과할 경우 이를 감지하여 출력노드에 인식시켜 주어 번-인 엑사이트(Exit)전압레벨을 엔트리레벨보다 낮추도록 함으로써 번-인 실험조건에서의 오실레이션 현상을 방지함과 아울러 보다 안정화된 조건에서 번인 실험을 할 수 있도록 한다.The present invention relates to an internal voltage generation circuit capable of detecting an external voltage at burn-in, and in the related art, burn-in experimental conditions are limited to chip operation, and are used for entry and exit. Since hysteresis is not considered, oscillation occurs when entering burn-in mode. Therefore, in the present invention, when the external voltage increasing in the internal voltage generating circuit exceeds a certain period, it detects this and recognizes the output node so that the burn-in exit voltage level is lower than the entry level. It prevents oscillation under the condition and allows burn-in experiments under more stable conditions.

Description

번-인시 외부전압 감지가 가능한 내부전압 발생회로Internal voltage generation circuit capable of detecting external voltage at burn-in

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 본 발명의 번-인시 외부전압 감지가 가능한 내부전압 발생회로도.4 is an internal voltage generation circuit capable of detecting an external voltage at burn-in of the present invention.

제5도는 제4도에서 버퍼의 상세회로도.5 is a detailed circuit diagram of the buffer in FIG.

Claims (3)

입력되는 제어신호에 따른 기준전압을 발생하는 기준전압 발생수단과, 상기 기준전압 발생수단에서 발생하는 기준전압에 따라 증가하는 외부전압이 일정구간을 초과할 경우 이를 래치하고 다시 외부전압이 일정구간으로 감소할 경우 그 차를 출력하는 번인 검출수단과, 상기 번인 검출수단으로 부터 출력되는 전압에 따른 기준전압을 출력하여 칩의 동작을 알리는 제어에 따라 스탠바이시엔 스탠바이용 차동증폭수단을 액티브시엔 액티브용 차동증폭수단을 동작시켜 전류를 공급하도록 하는 바이어스용 기준전압 발생수단으로 구성된 것을 특징으로 하는 번-인시 외부전압 감지가 가능한 내부전압 발생회로.When the reference voltage generating means for generating a reference voltage according to the input control signal and the external voltage increasing according to the reference voltage generated by the reference voltage generating means exceeds a certain period, the latch is latched again and the external voltage returns to a predetermined period. In case of decrease, the differential differential means for standby and standby is activated according to the control of burn-in detection means for outputting the difference and control of informing the operation of the chip by outputting a reference voltage according to the voltage output from the burn-in detection means. An internal voltage generation circuit capable of sensing an external voltage at burn-in, comprising: a reference voltage generating means for biasing the amplifying means to supply a current. 제1항에 있어서, 번인 검출수단은 입력되는 기준전압(Vref1)에 따라 동작하여 외부전압을 감지함과 아울러 그 감지전압이 소정값을 넘으면 래치하는 전압감지수단과, 상기 전압감지수단으로 부터 출력되는 전압을 버퍼링하여 출력하는 버퍼와, 상기 버퍼의 출력에 따라 온 또는 오프하여 생성된 번인감지 기준전압(Vrefb)이 소정레벨 이상이면 상기 전압감지수단으로 전달하고 정상이면 출력하는 번인기준전압 감지수단과, 상기 버퍼의 출력에 따른 펄스를 생성하여 상기 전압감지수단이 래치상태를 조절하도록 하는 펄스발생수단으로 구성된 것을 특징으로 하는 번-인시 외부전압 감지가 가능한 내부전압 발생회로.2. The burn-in detection unit according to claim 1, wherein the burn-in detection unit operates according to the input reference voltage Vref1 to sense an external voltage and outputs the voltage detection unit for latching when the detection voltage exceeds a predetermined value, and outputs from the voltage detection unit. A buffer for buffering and outputting a voltage to be output, and a burn-in reference voltage detecting means for outputting the burn-in detecting reference voltage Vrefb generated by turning on or off according to the output of the buffer to the voltage detecting means when the voltage is higher than or equal to a predetermined level. And a pulse generating means for generating a pulse according to the output of the buffer so that the voltage sensing means adjusts a latch state. 제2항에 있어서, 전압감지수단은 게이트가 접지측과 접속되고 소오스가 전원단자와 접속된 피모스트랜지스터(PM21)와 접지사이에 소정개의 엔모스를 직렬연결하고, 상기 접지에 소오스측에 접속된 엔모스트랜지스터(NM25)의 게이트는 번인기준전압 감지수단의 출력단과 접속하고 그의 드레인은 버퍼의 입력단에 접속함과 아울러 피모스트랜지스터(PM23)의 드레인측에 접속하며, 상기 피모스트랜지스터(PM23)의 게이트는 펄스발생수단에 접속하고, 전원단자(VCC)와 연결된 상기 피모스트랜지스터(PM23)의 소오스는 게이트와 접속하며, 상기 엔모스트랜지스터(NM21-NM24) 중 어느 하나의 소오스와 드레인사이에 쉬미트트리거 방식으로 피모스트랜지스터(PM22)를 접속하고 구성된 것을 특징으로 하는 번-인시 외부전압 감지가 가능한 내부전압 발생회로.3. The voltage sensing means according to claim 2, wherein a predetermined NMOS is connected in series between the PMOS transistor PM21 having a gate connected to the ground side and a source connected to the power supply terminal, and a ground, and connected to the source side to the ground. The gate of the NMOS transistor NM25 is connected to the output terminal of the burn-in reference voltage sensing means, and the drain thereof is connected to the input terminal of the buffer, and to the drain side of the PMOS transistor PM23, and the PMOS transistor PM23. ) Is connected to the pulse generating means, the source of the PMOS transistor PM23 connected to the power supply terminal VCC is connected to the gate, and between any one source and the drain of the NMOS transistors NM21 to NM24. The internal voltage generation circuit capable of detecting the external voltage at the time of burn-in, characterized in that the PMOS transistor (PM22) connected to the Schmitt trigger method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940029940A 1994-11-15 1994-11-15 Internal voltage generating circuit to detect the external voltage in burn-in KR0121146B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940029940A KR0121146B1 (en) 1994-11-15 1994-11-15 Internal voltage generating circuit to detect the external voltage in burn-in

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KR1019940029940A KR0121146B1 (en) 1994-11-15 1994-11-15 Internal voltage generating circuit to detect the external voltage in burn-in

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KR960018824A true KR960018824A (en) 1996-06-17
KR0121146B1 KR0121146B1 (en) 1997-12-04

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990055280A (en) * 1997-12-27 1999-07-15 윤종용 Monitor board supervision of burn-in test unit
KR100462101B1 (en) * 1997-10-25 2005-04-06 삼성전자주식회사 Burn in voltage control method
KR100505569B1 (en) * 1997-12-08 2005-10-19 삼성전자주식회사 Internal Voltage Generator for Synchronous DRAM Semiconductor Devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100462101B1 (en) * 1997-10-25 2005-04-06 삼성전자주식회사 Burn in voltage control method
KR100505569B1 (en) * 1997-12-08 2005-10-19 삼성전자주식회사 Internal Voltage Generator for Synchronous DRAM Semiconductor Devices
KR19990055280A (en) * 1997-12-27 1999-07-15 윤종용 Monitor board supervision of burn-in test unit

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