KR960016406B1 - Bus transferring apparatus between cpu and peripheral - Google Patents

Abstract

the first inverter inverting the phase of a bus grant signal outputted from a central processing unit(CPU); the first NAND gate performing a NAND operation of an address strobe signal(AS) from the CPU and the signal outputted from the first inverter; an OR gate performing an OR operation of the output of the first NAND gate and a bus request signal from a peripheral device; the second inverter inverting the phase of a bus grant signal from the peripheral device; a second NAND gate; the third NAND gate; a bus grant signal-generating means(100) generating the bus grant signal by comprising D flip-flops; a bus grant signal processing means(101) outputting the bus grant signal; and a bus grant acknowledge signal-generating means(102) including several bus grant acknowledge signal generators.

Description

Bus transfer between central processing unit and peripherals

1 is a block diagram of a conventional bus transfer device between a central processing unit and a peripheral device.

2 is a block diagram of a bus transfer device between the present invention and the central processing unit.

3 is a first embodiment of a bus permission signal generator of FIG.

4 is a second embodiment of the bus permission signal generator of FIG.

5A to 5B are input / output timing diagrams of the bus permission signal generator of FIG.

* Explanation of symbols for main parts of the drawings

100: bus permission signal generation unit 101: bus permission signal processing unit

102: bus permission recognition signal generator

The present invention relates to a bus arbitration device between a central processing unit (hereinafter, referred to as a CPU) and a peripheral device. In particular, the peripheral device is a bus controller even in a circuit composed of different devices. It also relates to a bus handover between a CPU and a peripheral that allows it to become a bus master and to control the appropriate bus pass even when the CPU is already executing instructions.

In general, the condition for the peripheral device to become a bus master includes first, a bus request signal for requesting a bus transfer to a CPU, and a second bus grant signal indicating a bus transfer permission from the CPU. After receiving the signal, a bus grant acknowledgment signal indicating whether the third bus is allowed or not is transmitted to the CPU.

A bus transfer device between a conventional CPU and a peripheral device which transfers a bus through such a path outputs a bus request signal and outputs a bus permission recognition signal upon receiving a bus permission signal, as shown in FIG. A bus transfer interface unit for transmitting the device 10 and various signals output from the peripheral device 10 to the CPU 30, and transmitting the various signals output from the CPU 30 to the peripheral device 10. And a CPU 30 that receives the bus request signal output from the bus transfer interface unit 20 and outputs a bus permission signal to the peripheral device according to the priority.

Referring to the operation of the bus transfer device between the conventional CPU and the peripheral device configured as described above in detail, when the peripheral device 10 needs to operate as a bus controller while the CPU 30 is managing and using the bus, The device 10 outputs a bus request signal.

Here, other peripheral devices also generate a bus request signal as described above.

The bus request signal output from the peripheral device 10 is transmitted to the CPU 30 through the bus transfer interface unit 20.

The CPU 30 transmits a bus grant signal to only one peripheral device according to the priority of the bus request signal transmitted from each peripheral device.

The bus permission signal output from the CPU 30 is transmitted to the selected peripheral device 10 through the bus transfer interface unit 20.

The peripheral device 10 receives the bus permission signal, and outputs a bus grant acknowledgment signal as a response signal. The bus permission recognition signal is the bus transfer interface unit 20 as described above. It is transferred to the CPU 30 through the bus transfer.

After that, as the bus is transferred, the peripheral device 10, which becomes a bus jurisdiction, performs a necessary operation.

On the other hand, when the bus transfer request signal (BUS Request) is input while the CPU 30 is executing the instruction, the CPU 30 is currently executing a command but the bus transfer permission signal Bus Transfer is transferred to the request signal Bus. Request is sent to the peripheral device that generated it.

For example, in the process of processing an interrupt, the CPU 30 transmits a bus transfer permission signal to a peripheral device when a bus transfer request signal is input.

At this time, the CPU 30 actually executes a residual command and transmits only a bus transfer permission signal to the peripheral device.

However, the conventional bus transfer device between the CPU and the peripheral device does not have any problem when it is composed of elements of the same series, but when it is composed of different series, that is, the peripheral which does not output a bus grant acknowledgment signal. In the case of a device, the bus permission recognition signal has to be generated externally instead of the peripheral device itself and has to be transmitted to the CPU.

For this reason, there is also an inconvenience in that a circuit for bus transfer using only a bus grant signal must be separately configured in a circuit configuration.

In addition, if the CPU is already in the instruction execution (for example, interrupt processing), when a bus transition request comes in, the CPU issues the bus transition permission signal while executing the instruction.

Therefore, at this moment, there are two masters, and only the peripheral processor receiving the bus is operating normally, and if the CPU receives the bus back, the instructions that were being processed before the transfer could be lost.

Accordingly, an object of the present invention is to provide a bus transfer device between a CPU and a peripheral device so that the peripheral device may be a bus controller even in a device composed of other series of devices.

It is another object of the present invention to provide a bus handover device between the CPU and the peripheral device so as to control the appropriate bus usage right even when the bus handover request signal is applied from the peripheral device while the CPU is executing an instruction.

The object of the present invention is a bus permission signal generator comprising a plurality of bus permission signal generators for generating a bus permission signal according to a bus request signal, a bus permission signal, an address strobe signal, and a clock signal output from each peripheral device and a CPU. Bus permission signal processing means for processing bus permission signals generated by a plurality of bus permission signal generators in said bus permission signal generation means according to a priority, and according to a bus permission signal generated by said bus permission signal processing means; This is achieved by configuring a bus permission recognition signal generating means comprising a plurality of bus permission recognition signal generators for generating a bus permission recognition signal, which will be described below in detail with reference to the accompanying drawings.

2 is a schematic diagram of a bus transfer device including a CPU and a peripheral device according to the present invention. As shown in FIG. 2, a bus request signal, a bus permission signal, an address strobe signal, and a clock signal output from each peripheral device and a CPU are shown. A bus permission signal generator 100 comprising a plurality of bus permission signal generators 100-1 to 100-N for generating a permission signal, and a plurality of bus permission signal generators 100 in the bus permission signal generator 100; A bus permission signal processing unit 100 for processing the bus permission signals generated in each of -1 to 100-N according to priority and a bus permission recognition signal according to the bus permission signal generated by the bus permission signal processing unit 101; It consists of a bus permission recognition signal generator 102 composed of a plurality of bus permission recognition signal generators 102-1 to 102-N.

In the above, one bus permission signal generator 100-1 in the bus permission signal generator 100 inverts the phase of the bus permission signal BG output from the CPU (not shown). ) And a first NAND gate 100-1b that negatively crosses the signal output from the first inverter 100-1a with the address strobe signal AS output from the CPU, and the first NAND gate 100-1b. OA gate (100-1c) for the logical sum of the output of the) and the bus request signal output from the peripheral device, a second inverter (100-1d) for phase-inverting the bus permission signal output to the peripheral device, and the second inverter The second NAND gate 100-1e and the output of the second NAND gate 100-1e that negatively multiply the signal output from 100-1d with the output value of the first NAND gate 100-1b; When the third NAND gate 100-1f negatively multiplies the output of the oragate 100-1c and the clock pulse LK input from the outside, the phase is raised. The D flip-flop 100-1g outputs the output of the third NAND gate 100-1f as the bus permission signal BG.

Referring to Figure 3 attached to the operation and effects of the bus transfer device between the present invention CPU and the peripheral device configured as described above in detail as follows.

First, the bus request signal BR generated from one peripheral device (not shown) is input to the first bus permission signal generator 100-1 in the bus permission signal generator 100.

In addition, a bus permission signal BG and an address strobe signal AS generated by a central processing unit (not shown in the drawing) are also input to the first bus permission signal generator 100-1 and the first bus permission signal generator The clock pulse CLK generated from the outside is input to 100-1 so as to process the respective signals.

Accordingly, the first bus permission signal generator 100-1 processes the signals BR, AS, GB, and CLK, respectively, to generate a bus grant signal, which is as follows.

As shown in FIG. 3, the bus permission signal BG output from the CPU is phase-inverted to the first inverter 100-1a and input to one input terminal of the first NAND gate 100-1b.

When the address strobe signal AS output from the CPU being the type force of the first NAND gate 100-1b is high (1), the entire circuit operates. The address strobe signal AS is high. Means that there is no operation on the current CPU, that is, the CPU can transfer the bus.

On the other hand, the bus request signal BR output from the peripheral device for which the bus is to be transferred is input to one input terminal of the oragate 100-1c, and is output by being ORed with the output value of the first NAND gate 100-1b.

In addition, the value output from the first NAND gate 100-1b is negatively multiplied by the bus permission signal phase-inverted through the second inverter 100-1d and the second NAND gate 100-1e. The value output from the second NAND gate 100-1e is negatively multiplied with the value output from the OR gate 100-1c to the third NAND gate 100-1f, and the resultant value is a D flip-flop ( 100-1g).

The D flip-flop (100-1g) outputs the input data as a bus grant signal (Bus Grant) when the clock pulse (CLK) input from the outside rises, and inputs it to the bus permission signal processor (101).

In addition, the bus permission signal corresponding to each peripheral device obtained through the above series of processes is also input to the bus permission signal processor 101.

Accordingly, the bus permission signal processing unit 101 has the highest priority according to the priority of the bus permission signals generated from the respective bus permission signal generators 100-1 to 100-N in the bus permission signal generator 101. The bus permission signal is output to one peripheral device corresponding to the bus permission signal.

On the other hand, the peripheral device receiving the bus permission signal does not generate a bus permission recognition signal by itself unlike the conventional art.

Therefore, in the present invention, the bus permission recognition signal generators 102-1 to 102-N are placed in front of each peripheral device so that the bus permission signals output from the bus permission signal processor 101 can be input in parallel.

In this way, the bus permission recognition signal generators 102-1 to 102-N recognize a corresponding bus permission signal when a bus permission signal is applied to a corresponding peripheral device in response to the bus permission signal generated by the bus permission recognition signal processor 101. FIG. The bus is transferred by generating a signal and applying it to the CPU.

FIG. 4 is another embodiment of the bus permission signal generator 100-1 in the bus permission signal generator 100 of the present invention, and is provided to the address strobe signal AS and the first inverter 100-1h generated by the CPU. The first and second gates 100-1j, which are logically multiplied by the bus permission signal BG, which has been inverted in phase, and the second inverter 100, which inverts and outputs the output signal of the first and gates 100-1j 1k), an OR gate 100-1m that logically combines the output signal of the second inverter 100-1k with the bus request signal BR generated from a peripheral device, and the second inverter 100-1k. Phase inverts the output signal of the second and gate (100-1n) and the output signal of the second and gate (100-1m) and the output signal of the D flip-flop (100-1s) The third inverter (100-1p) and the output signal of the third inverter (100-1p) and the output signal of the oragate (100-1m) to logically multiply An output of the third and fourth gates 100-1r and the fourth and second inverters 100-1r and 100-1r that phase-inverts the output signals of the third and gates 100-1q and 3rd gate 100-1q. A D flip-flop (100-1s) for receiving the signal as data and outputting the input data as a bus permission signal when the clock signal (CLK) output from the CPU rises; and the first through third outputs from the CPU. The fourth and gates 100-1t for ANDing the function code signals FC0 to FC2, and the fourth inverters 100-1u for inverting and outputting the output signals of the fourth and gates 100-1t. And a fifth and gate (100-1v) for ANDing the output signal (AD) of the fourth inverter (100-1u) and the output signal of the D flip-flop (100-1s), and the fifth end (5). The sixth inverter gate 100-1w outputs the output signal of the gate 100-1v by the phase inversion and outputs as a bus permission signal.

Hereinafter, the operation and effect of another embodiment of the present invention will be described in detail.

In fact, when the bus transfer signal BR is transmitted to the CPU, the CPU immediately generates the bus transfer permission signal BG.

In the normal case, that is, when the bus transfer request signal BR is input after the CPU completes the instruction execution, the CPU generates the bus transfer enable signal BG. The problem does not occur even if it is not used.

However, when the instruction is not completed, the CPU transfers the bus transfer permission signal to the peripheral device according to the bus transfer request signal BR, thereby causing a problem when the master becomes a peripheral device.

Therefore, in this case, even if the CPU generates the bus permission signal (BG), the bus must be transferred after completing the current instruction execution without actually transferring the bus right to the peripheral device.

In this case, the necessary signals are function code signals called FC0 to FC2, and the method of using this FC is as follows.

The CPU outputs the FC (FC0 ~ FC2) value high when interrupt processing, and waits until one of the signals transitions to the low level again.

When the FC value goes low, it means that the command being executed is completed.

Another practical embodiment of the present invention will be described with reference to FIGS. 4 and 5 with reference to the basic concept of the present invention.

First, as shown in FIG. 4, when a bus request signal BR as shown in FIG. 5C is input from the peripheral device to the CPU, the CPU generates a bus permission signal BG as shown in FIG. 5D. Output it.

In addition, the address strobe signal AS is output at the timing shown in FIG. 5B.

Accordingly, the bus permission signal generator 100-1 in the bus permission signal generator 100 inverts the bus permission signal BG to the first inverter 100-1h, and the phase inverted signal and the phase inverted signal. The address strobe signal AS is logically multiplied by the first and gates 100-1j, and the resultant phase is inverted to the second inverter 100-1k.

In addition, the phase inverted signal to the second inverter (100-1k) and the bus transfer request signal (BR) is logically multiplied by the oragate (100-1m) and output as a result signal.

In the case where the output signal of the oragate 100-1m becomes "low" (0), the bus request signal BR is low (0), the bus permission signal BG is low (0), and the address The strobe signal AS should be high (1).

When the address strobe signal AS is low (0), it means that the current CPU is executing another instruction.

If the above three conditions (BR = 0, BG = 0, AS = 1) are satisfied, the output signal of the oragate (100-1 m) is low.

On the other hand, the above-described output signal of the second and gate (100-1k) is input to one input terminal of the second or gate (100-1n), and the output value of the D flip-flop (100-1s) and the output is Phase inversion is performed at the third inverter gate 100-1p and is input to one input terminal of the third and gate 100-19.

In this case, since the above-described output signal of the oragate 100-1m is input to the type force terminal of the third and gate 100-19, the oragate 100-1m is multiplied by two inputs and outputs.

The output signal of the third and gates 100-19 is phase-inverted through the fourth inverter gate 100-1r and input to the D flip-flop 100-1s as data.

Accordingly, the D flip-flop 100-1s outputs the input data through the output terminal Q when the clock signal CLK generated from the CPU is at the rising edge.

At this time, when the address strobe signal AS is high (1), the output of the D flip-flop (100-1s) is high (1), the output high (1) signal is the second and gate 100 Feeding back to -1n), the output of the D flip-flop (100-1s) goes low.

On the other hand, when the address strobe signal AS is low (0), the output of the D flip-flop (100-1s) is low (0), and the output low (0) signal is the second and gate ( By feeding back to 100-1n), the output of the D flip-flop 100-1s transitions high.

However, it is unclear whether the address strobe signal AS transitions from the high 1 to the low 0 to perform another instruction of the CPU or to execute the instruction of a peripheral device that requests the transfer of the bus.

If the CPU is executing another instruction, that is, interrupt processing, the bus should not be transferred at this point.

During interrupt processing, the CPU transitions all of the function code signals FC0, FC1, and FC2 to a high level.

Accordingly, the fourth end gate 100-1t logically multiplies the above-described FC signals FC0, FC1, and FC2, and outputs a high signal as a result signal.

The fifth inverter gate 100-1u inverts the output signal of the fourth and gates 100-1t to the fifth and gate 100-1v by inverting the phase as shown in FIG. 5E.

Therefore, the output of the D flip-flop 100-1s is made high by the address strobe signal AS, but the final bus permission signal out is determined by the function code signals FC0, FC1, and FC2. It is done.

In other words, when the FC signals are all high (FC0 = 1, FC1 = 1, FC2 = 1, in which case the CPU is executing the instruction), the final output (out) goes low and the bus is not allowed. When the signal is completed, the FC value is shifted low so that the final output (out) becomes high to generate the actual bus transfer permission signal.

The bus transfer permission signal generated in this way is input to the bus permission signal processor 101.

In addition, the bus permission signal corresponding to each peripheral device obtained through the above series of processes is also input to the bus permission signal processor 101.

Accordingly, the bus permission signal processing unit 101 has the highest priority according to the priority of the bus permission signals generated from the respective bus permission signal generators 100-1 to 100-N in the bus permission signal generator 101. The bus permission signal is output to one peripheral device corresponding to the bus permission signal.

On the other hand, the peripheral device receiving the bus permission signal does not generate a bus permission recognition signal by itself unlike the conventional art.

Therefore, in the present invention, the bus permission recognition signal generators 102-1 to 102-N are placed in front of each peripheral device so that the bus permission signals output from the bus permission signal processor 101 can be input in parallel.

In this way, the bus permission recognition signal generators 102-1 to 102-N recognize the bus permission signal when the bus permission signal is applied to the peripheral device in response to the bus permission signal generated by the bus permission signal processor 101. FIG. The bus is transferred by generating a signal and applying it to the CPU.

As described in detail above, the present invention can generate a bus permission recognition signal even when a circuit is composed of other series devices, thereby stably transferring the bus.

In addition, when the CPU is executing the instruction, the bus permission signal is not actually generated by the function code signal, and the bus is transferred only after the CPU completes the instruction execution. There is an effect that it is possible to prevent the loss of instructions during execution of instructions generated by the transfer of the bus.

Claims (2)

One bus permission signal generator performs a phase inverting of the bus permission signal output from the central processing unit, and a first logic to negatively multiply the signal output from the first inverter with the address strobe signal output from the central processing unit. An OR gate for ORing the NAND gate, the output of the first NAND gate and the bus request signal output from the peripheral device, a second inverter for phase-inverting the bus permission signal outputted to the peripheral device, and the second inverter A second NAND gate that negatively multiplies the output signal with the output value of the first NAND gate, a third NAND gate that negatively multiplies the output of the second NAND gate and the output of the oragate, and an externally input clock pulse According to the present invention, it is composed of D flip-flop which delays the output of the third NAND gate by a predetermined time and outputs it as a bus permission signal. Bus permission signal generating means for generating a bus permission signal in accordance with a bus request signal and a bus permission signal, an address strobe signal and a clock pulse outputted from the central processing unit, and from a plurality of bus permission signal generators in the bus permission signal generating means. Bus permission signal processing means for processing each generated bus permission signal according to priority and outputting a bus permission signal, and a plurality of buses for generating a bus permission recognition signal according to the bus permission signal output from the bus permission signal processing means; A bus transfer device between a central processing unit and a peripheral device, characterized in that it comprises a bus permission recognition signal generating means including a permission recognition signal generator. 2. The bus terminal of claim 1, wherein the bus permission signal generating means comprises: a first end in which one bus permission signal generator logically multiplies an address strobe signal generated by the central processing unit with a bus permission signal phase-inverted by a first inverter; An OR gate performing a logic OR match between a gate, a bus request signal generated from the peripheral device, and an output signal of the first and gate phase-inverted by the second inverter gate, an output signal of the second inverter gate, and a D flip-flop A second end gate, which is logically ANDed with an output signal of the third gate; and a third end gate which is ANDed with the output signal of the oragate and the output signal of the second and gate phase-inverted through a third inverter gate; D outputting the output signal of the third and gate phase-inverted through the fourth inverter when the clock pulse output from the device rises; A flip-flop, a fourth end gate for ANDing the first to third functional signals generated from the central processing unit, an output signal of the D flip-flop and an output signal of the fourth end gate through a fifth inverter gate, And a fifth inverter gate for multiplying and a sixth inverter gate for outputting a bus permission signal by inverting the output signal of the fifth and gate phases.