KR960015934A - Charge Coupled Device and Manufacturing Method - Google Patents

Charge Coupled Device and Manufacturing Method Download PDF

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Publication number
KR960015934A
KR960015934A KR1019940026624A KR19940026624A KR960015934A KR 960015934 A KR960015934 A KR 960015934A KR 1019940026624 A KR1019940026624 A KR 1019940026624A KR 19940026624 A KR19940026624 A KR 19940026624A KR 960015934 A KR960015934 A KR 960015934A
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South Korea
Prior art keywords
insulating layer
electrodes
electrode
forming
oxide film
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KR1019940026624A
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Korean (ko)
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KR0151381B1 (en
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이경수
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문정환
금성일렉트론 주식회사
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Priority to KR1019940026624A priority Critical patent/KR0151381B1/en
Publication of KR960015934A publication Critical patent/KR960015934A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H01L27/14806—Structural or functional details thereof
    • H01L27/14812—Special geometry or disposition of pixel-elements, address lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/762—Charge transfer devices
    • H01L29/765—Charge-coupled devices
    • H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
    • H01L29/76866—Surface Channel CCD
    • H01L29/76883—Three-Phase CCD

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Electromagnetism (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

본 발명은 전하결합소자 및 그 제조방법에 관한 것으로, 물리적 성질이 다른 게이트 절연막들을 이용하여 반도체기판내에 최대전위분포의 차이를 유도헐 수 있도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge coupling device and a method of manufacturing the same, and to induce a difference in maximum potential distribution in a semiconductor substrate using gate insulating films having different physical properties.

본 발명은 반도체기판과, 상기 반도체기판상에 형성된 제1절연층, 상기 제1절연층상에 일정간격을 두고 형성된 제1전극, 상기 복수개의 제1전극들과 제1절연층 사이에만 형성되는 제2절연층, 상기 제1전극, 제1절연층 및 제2절연층의 노출된 전표면상에 형성되는 제3절연층, 그리고 상기 제3절연층의 표면중, 복수개의 제1전극들 사이에 해당하는 영역들에서만 형성되는 복수개의 제2전극들을 구비하는 전하결합소자(CCD)를 제공함으로써 믈리적 성질이 다른 절연막들로 게이트절연층을 형성하여 절연층의 유전율차이에 의해 반도체기판내에 최대전위분포의 차를 유도하여 간단한 공정에 의해 우수한 특성을 갖는 CCD를 얻을 수 있도록 한다.The present invention provides a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a first electrode formed at a predetermined distance on the first insulating layer, and formed only between the plurality of first electrodes and the first insulating layer. A second insulating layer formed on an exposed entire surface of the second insulating layer, the first electrode, the first insulating layer, and the second insulating layer, and a surface of the third insulating layer; By providing a charge coupled device (CCD) having a plurality of second electrodes formed only in the regions to be formed, the gate insulating layer is formed of insulating films having different physical properties. By inducing the difference, a CCD having excellent characteristics can be obtained by a simple process.

Description

전하결합소자 및 제조방법Charge Coupled Device and Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 본 발명에 의한 CCD구조도,4 is a CCD structure diagram according to the present invention;

제5도는 본 발명의 CCD에 인가되는 입력파형도,5 is an input waveform diagram applied to a CCD of the present invention,

제6도 및 제7도는 본 발명의 CCD전극 하부의 기판표면영역의 최대전위분포를 시뮬레이션한 결과를 나타낸 도면.6 and 7 show simulation results of the maximum potential distribution of the substrate surface region under the CCD electrode of the present invention.

Claims (8)

반도체기판과 ; 상기 반도체기판상에 형성된 제1절연층, 상기 제1절연층상에 일정간격을 두고 형성된 복수개의 제1전극, 상기 복수개의 제1전극들과 제1절연층사이에만 형성되는 제2절연층, 상기 제l전극, 제1절연층 및 제2절연층의 노출된 전표면상에 형성되는 제3절연층, 그리고 상기 제3절연층의 표면 중 복수개의 제1전극들 사이에 해당하는 영역들에서만 형성되는 복수개의 제2전극들을 구비함을 특징으로 하는 전하결합소자.Semiconductor substrates; A first insulating layer formed on the semiconductor substrate, a plurality of first electrodes formed at predetermined intervals on the first insulating layer, a second insulating layer formed only between the plurality of first electrodes and the first insulating layer, and A third insulating layer formed on the exposed entire surface of the first electrode, the first insulating layer and the second insulating layer, and formed only in regions corresponding to the plurality of first electrodes of the surface of the third insulating layer; A charge coupling device comprising a plurality of second electrodes. 제1항에 있어서, 상기 제1전극 하부의 절연층은 질화막이고 제2전극 하부의 절연층은 산화막일을 특징으로 하는 전하결합소자.The charge coupling device of claim 1, wherein the insulating layer under the first electrode is a nitride film and the insulating layer under the second electrode is an oxide film. 제1항에 있어서, 상기 제1전극 하부의 제1절연층과 제2절연층은 각각 산화막과 질화막이고, 제3절연층은 산화막임을 특징으로 하는 전하결합소자.The charge coupling device of claim 1, wherein the first insulating layer and the second insulating layer under the first electrode are an oxide film and a nitride film, respectively, and the third insulating layer is an oxide film. 제3항에 있어서, 상기 제1전극 하부의 산화막은 열산화공정에 의해 형성된 것이고 제2전극 하부의 산화막은 화학기상증착에 형성된 것임을 특징으로 하는 전하결합소자.4. The charge coupling device of claim 3, wherein the oxide film under the first electrode is formed by a thermal oxidation process and the oxide film under the second electrode is formed by chemical vapor deposition. 제1항에 있어서, 상기 반도체기판 표면부위에 형성된 기판과 반대도전형의 메몰채널영역을 더 포함하는것을 특징으로 하는 전하결합소자.The charge coupling device of claim 1, further comprising a buried channel region opposite to the substrate formed on the surface of the semiconductor substrate. 반도체기판상에 제1절연층을 형성하는 공정과, 상기 제l절연층상에 제1절연층과 물리적 성질이 다른 제2절연층을 형성하는 공정, 상기 제2절연층상에 제1도전층을 형성하는 공정과, 상기 제1도전층과 제2절연층을 함께 패터닝하여 복수개의 제1전극을 형성하는 공정, 기판전면에 상기 제2절연층과 물리적 성질이 다른 제3절연층을 형성하는 공정, 상기 제3절연층상에 제2도전층임 형성하는 공정, 상기 제2도전층을 패터닝하여 제1전극들 사이에 해당하는 영역들에 복수개의 제2전극을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 하는 전하결합소자의 제조방법.Forming a first insulating layer on the semiconductor substrate, forming a second insulating layer having different physical properties from the first insulating layer on the first insulating layer, and forming a first conductive layer on the second insulating layer. Forming a plurality of first electrodes by patterning the first conductive layer and the second insulating layer together; forming a third insulating layer having a different physical property from the second insulating layer on the front surface of the substrate; And forming a second conductive layer on the third insulating layer, and forming a plurality of second electrodes in regions corresponding to the first electrodes by patterning the second conductive layer. Method of manufacturing a charge coupled device. 제6항에 있어서, 제1절연층과 제3절연층은 산화막으로 형성하고 제2절연층은 질화막으로 형성하는 것을 특징으로 하는 전하결합소자의 제조방법.The method of claim 6, wherein the first insulating layer and the third insulating layer are formed of an oxide film and the second insulating layer is formed of a nitride film. 제7항에 있어서, 상기 제1절연층은 열산화공정에 의해 형성하고 제3절연층은 화학기상증착방법에 의해 형성하는 것을 특징으로 하는 전하결합소자의 제조방법.8. The method of claim 7, wherein the first insulating layer is formed by a thermal oxidation process and the third insulating layer is formed by a chemical vapor deposition method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940026624A 1994-10-18 1994-10-18 Method of manufacturing charge coupled device KR0151381B1 (en)

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KR1019940026624A KR0151381B1 (en) 1994-10-18 1994-10-18 Method of manufacturing charge coupled device

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KR1019940026624A KR0151381B1 (en) 1994-10-18 1994-10-18 Method of manufacturing charge coupled device

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KR960015934A true KR960015934A (en) 1996-05-22
KR0151381B1 KR0151381B1 (en) 1999-03-30

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